Multilayer printed-circuit board and semiconductor device

ABSTRACT

A multilayer printed-circuit board is provided which is formed by stacking one on the other a plurality of circuit boards, each including a hard insulative substrate having a conductor circuit formed on one or either side thereof, and having formed therein via-holes formed through the hard insulative substrate to extend to the conductor circuit and each filled with a conductive substance, with an adhesive applied between the plurality of circuit boards, and heating and pressing the circuit boards together. One of the outermost ones of the stacked circuit boards has formed on the surface thereof conductive bumps each positioned right above the via-hole and electrically connected to the via-hole, and the other outermost one of the stacked circuit boards has formed on the surface thereof conductive pin or balls each positioned right above the via-hole and electrically connected to the via-hole. This multilayer printed-circuit board is used as a package circuit board and electronic components such as LSI chip are mounted on it to form a semiconductor device. The multilayer printed-circuit board is used as a core substrate, and a build-up wiring layer is formed on one or either side of the core multilayer circuit board. Solder bumps are formed on the surface of one outermost conductor circuit of the build-up wiring layer and conductive pins or balls are provided on the surface of the other outermost conductor circuit of the build-up wiring layer. Thus, a multilayer printed-circuit board is provided on which wiring can be made densely and also electronic components can be mounted with a high density.

TECHNICAL FIELD

The present invention relates to a multilayer printed-circuit board inwhich wiring can advantageously be done with an ultra-high density, amultilayer-printed-wiring board obtained by forming a build-upprinted-wiring layer on the multilayer printed-circuit board, and asemiconductor device including semiconductor components mounted on themultilayer printed-circuit board or multilayer printed-wiring board.

The present invention relates more particularly to a multilayerprinted-circuit board formed by stacking a plurality of singe-sidedcircuit boards one on the other, each having a plurality of filledvia-hole formed therein, with an adhesive applied between them, andheating and pressing them together or by laminating a single-sidedcircuit board on either side of a double-sided circuit board as a corewith an adhesive applied between the single-side circuit boards anddouble-sided circuit board, and heating and pressing the circuit boardstogether, a multilayer printed-wiring board obtained by forming abuild-up wiring layer on at least one side of the multilayerprinted-circuit board, and a semiconductor device using the multilayerprinted-circuit board or multilayer printed-wiring board.

BACKGROUND ART

Along with the recent innovation of the electronic technology, theelectronic devices have been designed to have a reduced physical sizeand operate at a higher speed, and thus the package circuit board onwhich IC chips are mounted has been required to have a correspondinglyhigher packaging density due to a finer pattern and operate with acorrespondingly higher reliability.

Such a package circuit board is known from the disclosure in the monthlyjournal “Surface Mount Technology”, January issue, 1997. Thisconventional package circuit board has a build-up multilayer wiringlayer formed on either side of a multilayer core circuit board.

In the above conventional package circuit board, however, a conductorlayer in a multilayer core circuit board and build-up multilayer wiringlayer are connected to each other by providing on the surface of thecore multilayer circuit board an inner pad wired from through-holes andconnecting via-holes to the inner pad. Thus, the land of eachthrough-hole takes the form of a dumbbell or the like, the inner padhinders through-holes from being disposed with an improved higherdensity, and only a limited number of through-holes can be formed.Hence, if the core circuit board is formed multilayered to increase thewiring density, it is not possible to assure a sufficient electricalconnection between outer build-up wiring layers and conductor layers inthe multilayer core circuit board.

The Inventors of the present invention proposed a method for overcomingthe above-mentioned drawbacks of the prior art in the Japanese PatentApplication No. 10-15346 (Unexarnined Patent Publication No.214846/'99).

The multilayer printed-wiring board disclosed by the Inventors of thepresent invention in the above Unexamined Patent Publication No.214846/'99 includes a build-up wiring layer formed by stackinginterlinear insulative resin layers and conductor layers alternately oneon the other on a multilayer core circuit board having an innerconductor layer and connecting the conductor layers to each other byvia-holes, the core multilayer circuit board having formed thereinthrough-holes each filled with a filler, a conductor layer being formedto cover an exposed surface of the filler from the through-holes, thevia-holes being connected to the conductor layer, whereby thethrough-holes are disposed with an improved density and the conductorlayer can positively be connected to the conductor circuit in the coremultilayer circuit board via the through-holes disposed with the highdensity.

However, the through-hole in the multilayer printed-wiring board isformed by forming holes through a core multilayer circuit board using adrill or the like and by electroless-plating the wall surface and boardsurface of the drilled hole. Thus, when the precision and cost offorming the through-hole are taken in consideration, the lower limit ofthe opening diameter of such a through-hole is on the order of 300 μm.To realize the ultrahigh density of wiring demanded from the presentelectronic industries, there should desirably developed techniquescapable of attaining a smaller opening diameter of the through-holeranging from 50 to 250 μm and a smaller through-hole land pitch.

To meet the above demand, the Inventors of the present invention formeda core multilayer circuit board by preparing a plurality of circuitboards having a conductor circuit formed on one or either side of a coresubstrate made of a hard material and a plurality of filled via-holeformed through the core substrate to extend from the one side thereof tothe conductor circuit, by stacking the plurality of circuit boards oneon the other with an adhesive applied between them, and then heating andpressing of the circuit boards together. With this core multilayercircuit board, it was found that even with the no through-hole providedin the core multilayer circuit board, sufficient electrical connectionscan be made between the conductor circuits in the core multilayercircuit board, and conductor circuits in the core multilayer circuitboard and build-up wiring layers formed on the core multilayer circuitboard, by a plurality of filled via-hole formed in the core multilayercircuit board and those formed in the build-up wiring layer right abovethe core multilayer circuit board.

The multilayer printed-circuit board has various electronic componentsincluding a semiconductor chip such as LSI and the other mounted on theoutermost surface thereof. The methods of mounting the electroniccomponents include a pin mounting technology in which part holes intowhich terminals of the electronic component are to be introduced areformed in place on the conductor circuit formed on the outermost surfacewhile connection lands whose diameter is slightly larger than that ofthe part hole are formed around the part holes, and a group of leads ofthe electronic component is connected, by soldering, to the part holesand connection lands, and a surface mounting technology in which a creamsolder is applied to a land formed in place on the conductor circuit inadvance, terminals of an electronic component are placed in contact withthe cream solder and then the cream solder is made to reflow in anatmosphere maintained at the melting temperature of the solder toconnect the electronic component.

When any of such mounting methods is employed to connect an electroniccomponent, however, it is indispensable to form on the conductor circuita land having an appropriate diameter. Nevertheless, in case anincreased number of electronic components is to be mounted on themultilayer printed-circuit board because of the reduced physical sizesand higher functions of the recent electronic devices, the total area ofsuch lands has to be too large to neglect, which stands in the way ofattaining a higher packaging density.

Also, when soldering for connection of an electronic component, it isindispensable to previously apply a solder resist to the electroniccomponent in order to prevent a melted solder from flowing to anunintended position where such flow is not desirable and causing ashort-circuit, break or the like. Thus, the multilayer printed-circuitboard has to be designed for an extra gap between wires withconsideration given to a possible misregistration in the solder resistprinting, which also stands in the way of attaining the higher packingdensity.

SUMMARY OF THE INVENTION

Accordingly, the present invention has an object to overcome theabove-mentioned drawbacks of the prior art by providing a multilayerprinted-circuit board and multilayer printed-wiring board in whichwiring can be done with a high density and on which electroniccomponents can be mounted with a high density, and a semiconductordevice using the multilayer printed-circuit board and wiring board.

The Inventors of the present invention have made various studies toattain the above object, and worked out the following inventions whichwill be outlined herebelow:

(1) The above object can be attained by providing a multilayerprinted-circuit board formed by stacking one on the other a plurality ofcircuit boards, each including a hard insulative substrate having aconductor circuit formed on one or either side thereof, and havingformed therein at least one via-hole being a hole formed through thehard insulative substrate to extend to the conductor circuit and eachfilled with a conductive substance, with an adhesive applied between theplurality of circuit boards, and heating and pressing the circuit boardstogether,

one of the outermost ones of the stacked circuit boards having formed onthe surface thereof at least one conductive bump positioned right abovethe via-hole and electrically connected to the via-hole; and

the other outermost one of the stacked circuit boards having formed onthe surface thereof at least one conductive pin or ball positioned rightabove the via-hole and electrically connected to the via-hole.

(2) Also the above object can be attained by providing a multilayerprinted-circuit board formed by stacking one on the other:

a plurality of single-sided circuit boards, each including a hardinsulative substrate having a conductor circuit formed on one sidethereof, and having formed therein at least one via-hole being a holeformed through the hard insulative substrate to extend to the conductorcircuit and each filled with a conductive substance; and

a single-sided circuit board including a hard insulative substratehaving at least one conductor circuit formed on one side thereof and atleast one hole formed through the hard insulative substrate to extend tothe conductor circuit, with an adhesive applied between the single-sidedcircuit boards, and heating and pressing the single-sided circuit boardstogether,

one of the outermost ones of the stacked circuit boards having formed onthe surface thereof at least one conductive bump positioned right abovethe via-hole and electrically connected to the via-hole; and

the other outermost one of the stacked circuit boards having formed onthe surface thereof at least one conductive pin or ball positioned rightabove the via-hole and electrically connected to the via-hole.

Preferably in the multilayer printed-circuit board described in theabove paragraph (1), one of the outermost ones of the plurality ofcircuit boards should have formed on the surface thereof a solder resistlayer covering the conductor circuit, and right above the via-hole aconductive bump connecting to a conductive layer or via-hole exposedfrom a hole formed in the solder resist layer, and the other outermostcircuit board should have formed on the surface thereof a solder resistlayer covering the conductor circuit, and right above the via-hole aconductive pin or ball connecting to a conductive layer or via-holeexposed from a hole formed in the solder resist layer.

In the multilayer printed-circuit boards described in the aboveparagraph (1) or (2), the distance between the neighboring via-holesformed in each of the circuit boards should desirably be increased as itgoes from one of the circuit boards towards the other.

(3) Also the object can be attained by providing a semiconductor deviceincluding the above multilayer printed-circuit board described in theabove paragraph (1) or (2) and at least one electronic componentelectrically connected to the conductive bumps formed on one of theoutermost circuit boards of the multilayer printed-circuit board.

In the semiconductor device described in the above paragraph (3), it isdesirable that the circuit board on which at least one electroniccomponent is mounted should have a stiffer provided along thecircumference thereof and a chip capacitor should be electricallyconnected to the one of the via-holes formed in the outermost circuitboard opposite to that outermost circuit board on which the electroniccomponent is mounted and which is located in a position opposite to theposition where the electronic component is mounted.

(4) Also the above object can be attained by providing a semiconductordevice including a multilayer printed-circuit board formed by stackingone on the other a plurality of circuit boards, each including a hardinsulative substrate having at least one conductor circuit formed on oneor either side thereof, having formed therein at least one via-holebeing a hole formed through the hard insulative substrate to extend tothe conductor circuit and each filled with an electro-plating substance,and including at least one projecting conductor, each electricallyconnected to the via-hole, with an adhesive applied between theplurality of circuit boards, and heating and pressing the circuit boardstogether, and at least one electronic component such as LSI chip,electrically connected to the outermost circuit board of the multilayerprinted-circuit board,

one of the outermost ones of the stacked circuit boards having formed onthe surface thereof at least one conductive bump positioned right abovethe via-hole and each electrically connected to the via-hole, and theelectronic component being electrically connected to the conductivebumps;

the other outermost circuit board opposite to the outermost circuitboard on which the electronic component is mounted having provided onthe surface thereof at least one chip capacitor, each electricallyconnected to the via-hole positioned beneath the electronic component.

In the semiconductor device described in the above paragraph (4), thecircuit board on which the electronic component is mounted shoulddesirably have a board warp-preventive stiffener secured by bonding tothe circumference thereof.

(5) Also the above object can be attained by providing a multilayerprinted-circuit board including a core multilayer circuit board havingan inner conductor circuit, having formed on one or either side thereofa build-up wiring layer formed from interlaminar insulative resin layersand conductor layers alternately stacked one on the other, the conductorlayers being connected to each other by at least one via-hole,

the core multilayer circuit board being formed by stacking one on theother a plurality of circuit boards, each including a hard insulativesubstrate having at least one conductor circuit formed on one or eitherside thereof, and having formed therein at least one via-hole being ahole formed through the hard insulative substrate to extend to theconductor circuit and each filled with a conductive substance, with anadhesive applied between the plurality of circuit boards, and heatingand pressing the circuit boards together.

In the multilayer printed-circuit board described in the above paragraph(5), it is desirable that the build-up wiring layer should be formed oneither side of the core multilayer circuit board, the outermostconductor layer forming one of the build-up wiring layers have at leastone solder bump formed on the surface thereof and the other outermostconductor layer forming the other build-up wiring layer have at leastone conductive pin or ball formed on the surface thereof.

Also, according to the present invention, there is provided a multilayerprinted-wiring board suitable for use as a mother board, in which theoutermost conductor layers forming the build-up wiring layer are coveredeach with a solder resist layer and the outermost conductor layerexposed from the hole formed in the solder resist layer is formed as aconductor pad (or in the form of a connection terminal).

Also in the multilayer printed-circuit board described in the aboveparagraph (5), it is desirable that the build-up wiring layer should beformed on one side of the core multilayer circuit board, at least onesolder bump to be connected to an electronic component including asemiconductor chip such as LSI be provided right above the via-hole onthe surface of the outermost conductor layer of the build-up wiringlayer, and at least one conductive pin or ball to be connected to amother board be provided right above the filled via-hole on theconductor circuit exposed on the other side of the core multilayercircuit board. Also, it is desirable that the outermost conductor layerforming the build-up wiring layer and the other side of the coremultilayer circuit board should be covered with a solder resist layer,at least one conductor pad be formed on one of the outermost conductivelayers, each exposed from a hole formed in the solder resist layer, andat least one conductive pint or ball to be connected to a mother boardbe formed right above the filled via-hole on the conductor circuitexposed on the other side of the core multilayer circuit board.

In the multilayer printed-circuit boards described in the aboveparagraphs (1) to (5), the conductive substance should desirably be ametal-plating produced by electro-plating or a conductive pastecomprising metal particles and thermosetting or thermoplastic resin.

In the multilayer printed-circuit boards described in the aboveparagraphs (1) to (5), it is desirable that each circuit board formingthe core multilayer circuit board should have at least one projectingconductor provided in a position corresponding to the via-hole andelectrically connected to the via-hole and also the projecting conductorbe formed from a conductive paste.

Further in the multilayer printed-circuit boards described in the aboveparagraphs (1) to (5), it is desirable that a part of the via-holes inthe build-up wiring layer should be positioned right above those formedin the core multilayer circuit board and connected directly to thevia-hole.

Furthermore, in the multilayer printed-circuit boards described in theabove paragraphs (1) to (5), it is desirable that thesingle-/double-sided circuit board as a basic unit forming the coremultilayer circuit board should be formed from a selected one of hardsubstrate materials such as glass epoxy resin, glassbismaleimide-triazine resin, glass polyphenylene ether resin, aramidnon-woven fabric-epoxy resin and aramid non-woven fabric-polyimideresin. Also, the circuit board should desirably be formed from a glassepoxy resin of 20 to 100 μm in thickness and the filled via-hole shoulddesirably have a diameter of 50 to 250 μm.

Moreover, the via-hole in each circuit board should desirably be formedfrom a hole formed by illuminating the surface of the glass epoxy resinsubstrate with 1 to 50 shots of a carbon-dioxide gas laser whose pulseenergy is 0.5 to 100 mJ, pulse width is 1 to 100 μs, pulse interval is0.5 ms or more.

These objects and other objects, features and advantages of the presentintention will become more apparent from the following detaileddescription of the preferred embodiments of the present invention whentaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows one example of the stacked state of the single-sidedcircuit boards forming the multilayer printed-circuit board according tothe present invention;

FIG. 2 shows another example of the stacked state of the single-sidedcircuit boards forming the multilayer printed-circuit board according tothe present invention;

FIG. 3 shows a still another example of the stacked state of thesingle-sided circuit boards forming the multilayer printed-circuit boardaccording to the present invention;

FIG. 4 shows a yet another example of the stacked state of thesingle-sided circuit boards forming the multilayer printed-circuit boardaccording to the present invention;

FIGS. 5(a) to 5(g) show a part of the process of manufacturing thesinge-sided circuit board forming the multilayer printed-circuit boardaccording to the present invention;

FIGS. 6(a) to 6(f) show a part of the process of manufacturing thesinge-sided circuit board forming the multilayer printed-circuit boardaccording to the present invention;

FIG. 7 shows one embodiment board (including a the single-sided circuitboard and a double-sided circuit board) of the multilayerprinted-circuit according to the present invention;

FIG. 8 shows another embodiment board (including only a the single-sidedcircuit board) of the multilayer printed-circuit according to thepresent invention;

FIG. 9 explains the position of filled via-hole in the embodiment shownin FIG. 8;

FIG. 10 shows one embodiment of the semiconductor device according tothe present invention;

FIG. 11 shows another embodiment of the semiconductor device accordingto the present invention;

FIGS. 12(a) to 12(f) show a part of the process of manufacturing a stillanother embodiment (having a build-up wiring layer on one side of themultilayer core board) of the multilayer printed-circuit board accordingto the present invention;

FIGS. 13(a) to 13(c) also show a part of the process of manufacturingthe multilayer printed-circuit board;

FIGS. 14(a) to 14(b) also show a part of the process of manufacturingthe multilayer printed-circuit board;

FIGS. 15(a) to 15(f) show a part of the process of manufacturing a yetanother embodiment (having a build-up wiring layer formed on either sideof the multilayer core board) of the multilayer printed-circuit boardaccording to the present invention;

FIGS. 16(a) to 16(c) also show a part of the process of manufacturingthe multilayer printed-circuit board according to the present invention;

FIGS. 17(a) to 17(b) also show a part of the process of manufacturingthe multilayer printed-circuit board according to the present invention;and

FIG. 18 shows a variant of the embodiment shown in FIG. 17(b) (havingBGA and PGA disposed on the multilayer printed-circuit board in FIG.17(b)).

BEST MODE FOR CARRYING OUT THE INVENTION

(1) The present invention is characterized, according to the presentinvention, in that a plurality of single- or double-sided circuitboards, each formed as a basic composition from a hard insulativesubstrate and having at least one conductor circuit formed on one oreither side of the hard insulative substrate and at least one via-holebeing a hole formed through the hard insulative substrate to extend tothe conductor circuit and each filled with a conductive substance, isappropriately combined with each other or combined, as necessary, with acircuit board having formed therein at least one via-hole being a hole,each filled with a conductive substance, but having no conductorcircuit, they are stacked one on the other with an adhesive appliedbesetment them and hot pressed together to provide a multilayerprinted-circuit board as a package circuit board.

More specifically, an outermost one of the plurality of circuit boardsstacked one on the other and hot pressed together has formed on thesurface thereof at least one conductive bump positioned right above thevia-hole for connection to connection terminals of an electroniccomponent and electrically connected to the via-hole, and the otheroutermost circuit board has provided on the surface thereof at least oneconductive pin (PGA) or ball (BGA) positioned right above the via-holeand electrically connected to the via-hole so as to be connectable to aconnection hole or connection pad provided on a mother board.

(a) In case the above multilayer printed-circuit board is constructed offour single-side circuit boards A to D for example, the conductorcircuit is exposed on the surface of the circuit board A at oneoutermost position and the projecting conductor connected to thevia-hole is exposed on the surface of the circuit board D at the otheroutermost position, as shown in FIG. 1 for example. As shown in FIG. 2for example, the conductor circuit is exposed on the surface of each ofthe circuit boards A and D located at the outermost positions,respectively.

(b) Also, in case the multilayer printed-circuit board is constructed ofthree circuit boards A, B and C and a double-sided circuit board E forexample, the circuit boards A and C located at the outermost positions,respectively, have their respective conductor circuits exposed on thesurfaces thereof as shown in FIG. 3 for example.

(c) Further, in case the multilayer printed-circuit board is constructedof three circuit boards A, B and C and a circuit board E having noconductor circuit for example, the circuit boards A and F located at theoutermost positions, respectively, have exposed on the surfaces thereoftheir respective projecting conductors connected to the via-holes,respectively, as shown in FIG. 4 for example.

The multilayer printed-circuit board may be constructed otherwise thanin any of the examples of multilayer printed-circuit board construction(a) to (c). The portion of the conductor circuit of the outermostcircuit boards, located right above the via-hole, may be formed as aconductor pad, and the exposed portion of the projecting conductorexposed on the surface of the outermost circuit board be formed as aconductor pad spreading circularly on the surface of the insulativesubstrate, as a result of melting of the exposed portion during the hotpressing.

Preferably in the construction of the multilayer printed-circuit boardshown in FIG. 1, an appropriate solder is supplied to form, on theconductor circuit exposed on the surface of the topmost circuit board,solder bumps which are to be connected to an electronic componentincluding semiconductor chip such as LSI, and the conductor pads formedfrom the projecting conductors in the position corresponding to thevia-holes on the bottommost circuit board have provided thereon T-shapedpins or solder balls which are to be connected to a connector orconnection pad on a mother board.

Also, an appropriate solder may be supplied onto the conductor circuitexposed on the surface of the outermost circuit board to form on theconductor pad formed from the projecting conductor in a positioncorresponding to the via-hole in the bottommost circuit board a solderbump to which the T-shaped pin or solder ball.

In any of the constructions of the multilayer printed-circuit board, thesolder bump will be formed on the conductor pad formed on a portion ofthe conductor circuit of the outermost one of the circuit boards or onthe conductor pad formed from the projecting conductor located rightabove the via-hole, and the T-shaped pin or solder ball will be providedon the conductor pad formed from the projecting conductor right abovethe via-hole, exposed on the surface of the other outermost circuitboard or on the conductor pad formed on the portion of the conductorcircuit.

According to a further aspect of the present invention, a solder resistlayer may be provided on the surface of the outermost one of the circuitboards to cover the conductor circuit of the circuit board, andconductor bumps to be connected to the conductor layer or via-holesexposed in a hole formed in the solder resist layer may be formed rightabove the via-holes, respectively. Also, a solder resist layer may beprovided also on the surface of the other outermost circuit board tocover the conductor circuits of the circuit board, and at least oneconductive pin or ball to be connected to the conductor layer orvia-hole exposed in a hole formed in the solder resist layer may beformed right above the via-hole.

Because of the above multilayer printed-circuit board construction,since the filled via-holes are provided highly densely in the multilayerprinted-circuit board and the conductive pin or ball is provided rightabove the one of the via-holes provided with a high density, exposed onthe surface of the outermost circuit board, wiring layers in themultilayer printed-circuit board can be connected over a shortest lengthto an electronic component including a semiconductor chip such as LSIand a mother board via the conductive bump, pin or ball. Thus, a highdensity of wiring can be attained.

Further, the multilayer printed-circuit board according to the presentinvention is advantageous in that since it is formed from stackedsingle- or double-sided circuit boards each as basic composition, athermal expansion-caused crack or delamination originating in theinterlaminar boundary will not easily take place and so the temperaturecycling test proves its high reliability.

Also, advantageously in a multilayer printed-circuit board using onlysingle-sided circuit boards according to the present invention, warpwill not easily occur whether wiring is formed or not therein.

Furthermore, in the above embodiment, since the conductive bump, pin orball is formed right above the via-hole exposed on the surface of theoutermost circuit board of the multilayer printed-circuit board, nosolder resist layer should necessarily be formed as in the prior art.This is because the insulation layer of the outermost circuit boardfunctions as the solder resist.

(2) Also the multilayer printed-circuit board is characterized,according to the present invention, in that the outermost one of theplurality of stacked circuit boards has formed on the surface thereof atleast one conductive bump positioned right above the via-hole and eachelectrically connected to the via-hole and the other outermost circuitboard has no conductive substance filled in the hole formed therein andhas provided thereon at least one conductive pin or ball electricallyconnected to the conductor circuit thereof.

Because of the above construction of the multilayer printed-circuitboard, the outermost one of the single-sided circuit boards forming themultilayer printed-circuit board functions as a reinforcing plate havingno filled via-hole. This is because the via-hole is smaller than theinner via-land and thus the insulation layer of the outermost circuitboard retains the circumference of the via-land while the via-hole isbeing formed. Further, since the conductive pin or ball is provided inthe hole formed in the circuit board so as to electrically be connectedto the conductor circuit, no solder resist layer is required.

(3) Also the semiconductor device is characterized, according to thepresent invention, in that the electronic component such as an LSI iselectrically connected to the conductive bumps formed on the outermostcircuit board of the multilayer printed-circuit board (1) or (2).

Because of the above construction of the semiconductor device, theconductive bump can be kept flat, so no connection or poor connectionwill take place between the conductive bumps and electronic components.

In the semiconductor device, it is desired that the circuit board onwhich at least one electronic component is to be mounted should have astiffener along the circumference thereof to enclose each of theelectronic components, and a chip capacitor should be connected directlyto one of the via-holes formed in the outermost circuit board oppositeto the electronic component mounting circuit board, which is positionedopposite to the position where the electronic component is mounted.

Because of the above construction of the multilayer printed-circuitboard, the distance between the electronic component such as LSI and thechip capacitor can be minimized and the loop inductance between them canbe reduced.

(4) The semiconductor device including a multilayer printed-circuitboard formed by stacking together, and heating and pressing, a pluralityof single-sided circuit boards in which filled via-holes are formed byelectro-plating, and electronic components such as LSI chipselectrically connected to the outermost circuit board of the multilayerprinted-circuit, the semiconductor device is characterized, according tothe present invention, in that:

the outermost one of the circuit boards has formed on the surfacethereof at least one conductive bump each positioned right above thevia-hole and connected electrically to the via-hole, the electroniccomponent is electrically connected to the conductive bumps via solderballs, and the other outermost circuit board opposite to the circuitboard on which the electronic component is to be mounted has provided onthe surface thereof at least one chip capacitor each electricallyconnected to the via-hole positioned beneath the position of theelectronic component.

Because of the above construction of the semiconductor device, thedistance between the electronic component such as LSI and the chipcapacitor can be minimized and the loop inductance between them can bereduced.

In the above semiconductor device, there should desirably be fixed, bybonding, along the circumference of the circuit board on whichelectronic components are to be mounted, a stiffener to prevent theentire circuit board from warping due to a difference in coefficient ofthermal expansion from one material to the other of the circuit board.

The stiffener should desirably be formed from a glass-resin compositematerial such as BT, FR4 or FR5, a metallic material such as copper, orthe lie and disposed to enclose the electronic component mounted on thecircuit board.

(5) The multilayer printed-circuit board is characterized, according tothe present invention, in that a plurality of single- or double-sidedcircuit boards, each formed as a basic composition from a hardinsulative substrate and having at least one conductor circuit formed onone or either side of the hard insulative substrate and at least onevia-hole being a hole formed through the hard insulative substrate toextend to the conductor circuits and each filled with a conductivesubstance, is stacked one on the other and hot pressed together and thatthe multilayer printed-circuit board thus provided is used as a coremultilayer circuit board and a build-up wiring layer is formed on one oreither side of the core multilayer circuit board.

In the embodiment in which the build-up wiring layer is formed on eitherside of the core multilayer circuit board, an interlaminar insulativelayer and conductor circuit are stacked alternately on either side ofthe core multilayer circuit board and the conductor circuits areelectrically connected to each other by the via-holes. At least a partof the surface of one conductor circuit located at the outermostposition of the build-up wiring layer is formed as a conductor pad, anda conductive bump such as solder bump is formed on the conductor pad soas to be connectable to the connection terminal, conductive pin or ballof the electronic component, while at least a part of the surface of theother conductor circuit located at the outermost position of thebuild-up wiring layer is formed as a conductor pad, and a conductor pinor ball is disposed on the conductor pad so as to be connectable to theconnection hole (connector) or connection pad on a mother.

In the above embodiment, a solder resist layer is provided to cover theconductor circuit located at the outermost position of the build-upwiring layer, a part of the conductor circuit, exposed from a holeformed in the solder resist layer is formed as a conductor pad, and aconductive bump, pin or ball is disposed on each conductor pad, tothereby form a multilayer printed-circuit board for a package circuitboard suitable for mounting electronic components thereon.

Also in the above embodiment, the solder resist layer is provided tocover the conductor circuit located at the outermost position of thebuild-up wiring layer and the part of the conductor circuit, exposed inthe hole formed in the solder resist layer, is formed as the conductorpad, whereby a multilayer printed-circuit board for a mother board canbe provided. In this embodiment, a connector for electrical connectionto the package circuit board should desirably be provided on theconductor pad as necessary.

Similarly, in the embodiment in which the build-up wiring layer isformed on one side of the core multilayer circuit board, at least a partof the surface of one circuit board located at the outermost position ofthe build-up circuit is formed as a conductor pad, and a conductive padsuch as a solder bump is formed on the conductor pad as to beconnectable to the connection terminal or conductive pin or ball of theelectronic component, while at least a part of the surface of theconductor circuit at the side of the core multilayer circuit board whereno build-up wiring layer is formed is formed as a conductor pad, and aconductive pin or ball is disposed on the conductor pad so as to beconnectable to the connection hole (connector) or connection pad on amother board.

Because of the construction of each of the above embodiments, it isunnecessary to provide through-holes in the core multilayer circuitboard, so the pad such as land can be disposed more freely. Thus, thefilled via-holes can be provided at a higher density. The outer build-upwiring layer can securely be connected to the conductor circuit in thecore multilayer circuit board via the via-holes formed at a high densityand thus wiring can also be made highly densely. Further, a high densityof the wiring within the core multilayer circuit board can be attained.

Moreover, since the via-holes are formed at a high density in thebuild-up wiring layer and a conductive bump, pin or ball is disposed onthe conductor pad exposed in the one of the densely formed via-holes inthe outermost interlaminar insulative resin layer, the build-up wiringlayer in the multilayer printed-circuit board is connected to anelectronic component including a semiconductor chip such as LSI and amother board via the conductive bumps, pins or balls using a shortestwire, whereby a high density wiring and high density mounting ofelectronic components can be attained.

In the multilayer printed-circuit boards and semiconductor devicedescribed in the above paragraphs (1) to (5), the insulative substrateused in the double/single-sided circuit boards forming the multilayerprinted-circuit board is not any semi-hard prepreg but a hard insulativesubstrate formed from a completely cured resin. When a copper foil isapplied to the insulative substrate of such a material by pressing, thefinal thickness of the insulative substrate will not vary due to theforce of pressing, so the misregistration of the via-hole can beminimized and the vialand diameter can be reduced. Therefore, the wiringpitch can be reduced and wiring density can be improved. Further, sincethe thickness of the substrate can be kept constant, laser illuminationconditions can easily be set when a hole for a filled via-hole is formedby laser beam machining.

The insulative resin substrate should preferably be formed from aselected one of hard substrate materials such as glass epoxy resin,glass bismaleimide-triazine resin, glass polyphenylene ether resin,aramid non-woven fabric-epoxy resin and aramid non-wovenfabric-polyimide resin, and most preferably be formed from the glassepoxy resin.

The thickness of the insulative substrate should desirably be 20 to 600μm to assure a sufficient insulation performance. If the thickness isless than 20 μm, the substrate will have a lower strength and thus bedifficult to handle and the reliability of its electrical insulationperformance will be lower. If the thickness is over 600 μm, it will bedifficult to form a hole for a fine via-hole and the substrate thicknessitself will be increased.

The hole for a via-hole should desirably be formed in the glass epoxysubstrate having a thickness within the above range by emitting to theglass epoxy substrate irradiating 1 to 50 shots of a carbon-dioxide gaslaser whose pulse energy is 0.5 to 100 mJ, pulse width is 1 to 100 μs,pulse interval is 0.5 ms or more. The hole diameter should desirably bewithin a range of 50 to 250 μm because a diameter of less than 50 μmwill lead to a difficulty of filling of a conductive substance into thehole and a lower reliability of the electrical connection while adiameter of more than 250 μm will lead to a difficulty of a high densitywith which the via-holes are formed.

It is desired that before forming the hole with a carbon-dioxide gaslaser, a resin film should be attached to a side of the insulativesubstrate opposite to the side on which the conductor circuit is to beformed and the side be illuminated with the laser from on the resinfilm.

The resin film serves as a protective mask when filing a metal-platinginto the desmeared hole for a via-hole by electro-plating, and also as aprinting mask to form a projecting conductor right above themetal-plating layer in the via-hole.

The resin film should desirably be formed from a polyethyleneterephthalate (PET) film whose adhesive layer is 1 to 20 μm in thicknessand whose thickness is 10 to 50 μm.

The reason for the above is that since the height of the projectingconductor depends upon the thickness of the PET film, a thickness ofless than 10 μm will result in an excessively low projecting conductorwhich will cause a poor connection while a thickness of more than 50 μmwill result in an excessive spreading of the projecting conductor at theboundary of connection and hence in an impossibility to form a finepattern.

The conductive substance to be filled in the hole formed through theinsulative substrate should preferably be a conductive paste or ametal-plating formed by electro-plating.

For simplification of the filing process, reduction of the manufacturingcost and improvement of the field, a conductive paste is suitably usableto fill the via-hole. For an improved reliability of the electricalconnection, a metal-plating formed by electro-plating, such as platingof tin, silver, solder, copper/tin, copper/silver or the like shouldpreferably be used, and the hole should most preferably be filled withan electrolytic copper.

The hole thus filled with the conductive substance forms a via-holewhich electrically connects conductor circuits formed on the insulativesubstrates to each other. In the embodiments of the multilayerprinted-circuit board as a package circuit board and semiconductordevice using the package circuit board according to the presentinvention, via-holes formed in each of circuit boards stacked one on theother are formed so that the distance between neighboring via-holes isshortest in the outermost circuit board on the side of the multilayerprinted-circuit board on which electronic components such as LSI chipare to be mounted while the distance is longest in the other outermostcircuit board on the side of the multilayer printed-circuit board atwhich the multilayer printed-circuit board is to be connected to amotherboard. That is, the density with which the via-holes are formed ineach of the stacked circuit boards should preferably be smaller from thecircuit board on which the electronic components such as LSI chip are tobe mounted towards the circuit board at which the multilayerprinted-circuit board is to be connected to the mother board. With thisconstruction of the multilayer printed-circuit board, the wires can berouted more freely.

The conductor circuit formed on one or either side of the insulativesubstrate should preferably be formed from a copper foil by hot-pressingof a copper foil of 5 to 18 μm in thickness laid under a adhesive resinlayer kept in a semi-hard state and then appropriately etching thecopper foil.

The above hot pressing is effected at an appropriate temperature andunder an appropriate pressure, and more preferably under a reducedpressure, to cure only the semi-hard adhesive resin layer. Thus thecopper foil can be securely attached to the insulative resin layer, sothe manufacturing time can be shortened as compared with theconventional circuit board using the prepreg.

The circuit board having such a conductor layer formed on either side ofthe insulative substrate can be used as a core of the multilayerprinted-circuit board, and there should preferably be formed on thesurface of the substrate corresponding to each via-hole lands (pads) asa part of the conductor circuit to have a diameter within a range of 50to 250 μm.

The single-side circuit board having a conductor circuit formed on oneside of the insulative substrate is used not only as a circuit board tobe stacked with the double-sided circuit board but only the single-sidedcircuit boards may be stacked one on the other to form a multilayerprinted-circuit board.

In such a single-sided circuit board, a projecting conductor shouldpreferably be formed right above a filled via-hole.

The projecting conductor should preferably be formed from a conductivepaste or a metal which melts at a low temperature. Since the conductivepaste or low melting-point metal will thermally be deformed in theprocess in which circuit boards are stacked one on the other togetherand hot pressed, differences in height of the conductive substancefilled in the via-holes and metal-plating layers can be reduced, so poorconnection can be prevented from taking place, whereby a multilayerprinted-circuit board whose electrical connection is highly reliable canbe provided.

The projecting conductor can be formed from the conductive substancefilled in the via-hole, for example, the conductive paste, and in thesame filling process.

As having been described in the foregoing, the conductive bump is formedright above the via-hole on the surface of a one, of the outermostcircuit boards of the multilayer printed-circuit board, located on theside of the multilayer printed-circuit board, formed by stacking one onthe other, and heating and pressing, on which electronic components suchas LSI chip are to be mounted. The conductive bump is formed in adot-matrix pattern or in a matrix pattern slightly shifted from thedot-matrix pattern, for example.

Also, the conductive pin or ball is formed right above the via-hole onthe surface of the other one of the outermost circuit boards, which isto be connected to a mother board. The conductive pin or ball is formedin a dot-matrix pattern or in a matrix pattern slightly shifted from thedot-matrix pattern similarly to the conductive bump.

How to make the multilayer printed-circuit board and semiconductordevice using the former, according to the present invention, will bedescribed below with reference to the accompanying drawings.

(A) Forming the Circuit Board for Stacking

(1) For making the multilayer printed-circuit board according to thepresent invention, an insulative substrate 10 having a copper foil 12attached to one side thereof is used as a starting material for acircuit board being a basic unit of the multilayer printed-circuitboard.

The insulative substrate 10 is formed from a hard insulative basematerial selected from glass epoxy resin, glass bismaleimide-triazineresin, glass polyphenylene ether resin, aramid nonwoven fabric-epoxyresin and aramid nonwoven fabric-polyimide resin. Of these materials,the glass epoxy rein should be used most preferably.

The insulative substrate 10 should desirably be 20 to 600 μm inthickness for the following reason. That is, if the thickness is lessthan 20 μm, the substrate 10 will have a lower strength and thus bedifficult to handle and the reliability of its electrical insulationperformance will be lower; on the other hand, if the thickness is over600 μm, it will be difficult to form fine via-holes and fill aconductive substrate in the via-holes and the substrate thickness itselfwill be increased.

The copper foil 12 should desirably be 5 to 18 μm in thickness for thereason that when a laser machining (as will further be described later)is used to form a hole for a via-hole in the insulative substrate, ifthe copper foil 12 is too thin, the laser will penetrate through itwhile if the copper foil 12 is too thick, it will be difficult to form,by etching, a conductor circuit pattern of which the wire width is verysmall.

Especially, a prepreg formed from a glass cloth having an epoxy resinimpregnated therein and in a B stage (semi-hard state) should preferablybe used as the insulative substrate 10 and the prepreg and the copperfoil 12 should preferably be stacked on each other and heated andpressed together to provide a single-sided coppered laminate. The reasonwhy the single-sided coppered laminate is preferable is that while thelaminate is being processed after the copper foil 12 is etched, thewiring pattern and via-hole position will not deviate. Namely, thepositioning precision is assured to be high.

(2) Next, to make a multilayer printed-circuit board having a conductorlayer formed on either side thereof, a protective film 14 is attached tothe surface of the insulative substrate 10 opposite to the side on whichthe copper foil 12 has been attached. See FIG. 5(a).

The protective film 14 is used as a printing mask for a conductive pastewhich forms the projecting conductor which will further be describedlater. For example, a polyethylene terephthalate (PET) film having anadhesive layer provided on the surface thereof is usable as theprotective film 14.

In the PET film, namely, the protective film 14, the adhesive layershould be 1 to 20 μm thick and the film itself be 10 to 50 μm thick.

(3) Further, a laser of carbon-dioxide gas is irradiated to the PET film14 over the insulative substrate 10 to form a hole 16 through the PETfilm 14 to extend from the surface of the insulative substrate 10 to thecopper film 12 (or conductor circuit patter). See FIG. 5(b).

The laser machining should desirably be effected with 1 to 50 shots of alaser having a pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 μsand a pulse interval of 0.5 ms or more, emitted from a pulse-oscillationtype carbon-dioxide gas laser beam machine.

The via-hole diameter thus formed by the laser machining shoulddesirably be 50 to 250 μm.

(4) To remove the resin residue on the wall and bottom of the hole 16formed in the above step (3), a desmearing process is done.

The desmearing is an oxygen plasma discharging, corona discharging,ultraviolet laser machining or excimer laser machining. Especially, theultraviolet laser or excimer laser should desirably be irradiated intothe hole 16 to remove the smear because this method will assure a highreliability of the connection.

For example, when an ultraviolet laser using YAG third harmonic is usedfor this desmearing, the oscillating frequency should desirably be 3 to15 kHz, pulse energy be 0.1 to 5 mJ and the number of shots be 5 to 30.

(5) Next, the desmeared substrate is plated with electrolytic copperusing the copper foil 12 as a plating lead and under the followingconditions to fill the hole 16 with an electrolytic copper-plating 18,thereby forming a filled via-hole 20. See FIG. 5c. As a result of thisplating, a small clearance into which a conductive paste 22 which willfurther be described later is to be filled, will remain in an upperportion of the hole 16, and the electrolytic copper-plating 18 is filledinto the clearance.

Electrolytic Copper Plating Solution

CuSO₄ · 5H₂O 65 g/l Leveling agent (HL by ATOTEK) 20 ml/l Sulfuric acid220 g/l Brightening agent (UV by ATOTEK) 0.5 ml/l Chlorine ion 40 ppm

Electro-plating Conditions

Bubbling 3.0 liters/min Current density 0.5 A/dm² Set current value 0.18A Plating length of time 130 min

(6) A clearance or concavity in the hole 16, having not been filled withthe electrolytic copper-plating 18 in the above step (5), is filled withthe conductive paste 22 taking the protective film 14 as the printingmask to form a conductive portion 24 (will be referred to as “projectingconductor” hereafter) projected for the thickness of the protective film14 from the insulative substrate 10. See FIG. 5(d).

(7) Next, an adhesive layer 26 is formed on the surface of theinsulative substrate 10 including the projecting conductor 24. See FIG.5(e). The adhesive layer 26 is in a semi-hard state (B-stage) to attachthe copper foil from which a conductor circuit patter is to be formed.It should preferably be an epoxy resin varnish and have a thickness of10 to 50 μm.

(8) A copper foil 28 is heated and pressed to the surface of theinsulative substrate 10 having the adhesive layer 26 provided thereon inthe above step (7) to cure the adhesive layer 26. See FIG. 5(f).

At this time, the copper foil 28 is attached to the insulative substrate10 with the cured adhesive layer 26 thereunder, and the projectingconductor 24 and copper foil 28 are thus electrically connected to eachother. The copper foil should desirably be 5 to 18 μm thick.

(9) Next, an etching protective mask is attached to each of the copperfoils 12 and 28 already attached to either side of the insulativesubstrate 10, and is covered with a predetermined circuit pattern mask.Thereafter, the insulative substrate 10 is subjected to etching to formconductor circuits 30 and 32 (including vialands). See FIG. 5(g).

In this step, first a photosensitive dry film is attached to the surfaceof each of the copper foils 12 and 28, it is exposed along apredetermined circuit pattern and developed to form an etching resist,and the metal layer on which the etching resist is not formed is etchedto form the conductor circuit patterns 30 and 32 including the vialands.

The etching solution used in the above process should preferably be atleast one selected from solutions of sulfuric acid-hydrogen peroxide,persulfate, cupric chloride and ferric chloride.

In a pre-processing step for forming the conductor circuits 30 and 32 byetching the copper foils 12 and 28, the entire surface of the copperfoil can be pre-etched to reduce the foil thickness to 1 to 10 μm, morepreferably, to 2 to 8 μm for easy formation of a fine pattern.

The vialand as a portion of the conductor circuit has an inside diameterwhich is substantially same as the via-hole diameter. The outsidediameter of the vialand should preferably be within a range of 50 to 250μm.

FIG. (10) Next, the surfaces of the conductor circuits 30 and 32 formedin the step (9) are roughened as necessary (the roughened surface is notillustrated) to form a double-sided circuit board 34.

The surface roughening is effected to improve the adhesion with theadhesive layer and prevent delamination during multilamination.

The surface roughening is done for example by soft etching, blackening(oxidation)-reduction, forming a needle-like platingcopper-nickel-phosphorus alloy (INTERPLATE by Ebara-Yujilite) orroughening with an etching solution “MecEtchbond” (by Mec).

In this embodiment, the roughened layer should preferably be formedusing an etching solution. For example, the surface of the conductorcircuit may be roughened by etching using an etching solution preparedfrom a mixed solution of cupric complex and organic acid. Such anetching solution can solve the copper-made conductor circuit pattern inthe presence of oxygen as in spraying or bubbling, and the solvingreaction is estimated to proceed as follows:

Cu+Cu(II) An→2Cu(I)An/ ₂

2Cu(I) An/₂+n/4O₂+nAH (aeration)→2Cu(II) An+n/2H₂O

where A: Complexing agent; n: Coordination number.

As shown above, the cuprous complex is solved under the action of theacid and couples with the oxygen to produce cupric complex which willcontribute to the oxidation of the copper again. The cupric complex usedin the present invention should preferably be a cupric complex of anyone of azoles. The etching solution of the organic an acid-cupriccomplex can be prepared by solving in water the cupric complex of anazole and organic acid (halogen ion as necessary).

The double-sided circuit board as basic composition of the multilayerprinted-circuit board according to the present invention is made byeffecting the above steps (1) to (10).

(11) Next, to make a single-side circuit board to be stacked on each ofthe front and rear sides of the above-mentioned double-sided circuitboard, first an etching protective film is attached to a copper foil 12(see FIG. 6(a)) attached to one side of an insulative substrate 10 andthen covered with a predetermined circuit pattern mask. Thereafter, thecopper foil 12 is etched to form a conductor circuit 40 (includingvialands). See FIG. 6(b).

In the above process, first, a photosensitive dry film resist isattached to the copper foil 12, the resist is exposed and developedalong the predetermined circuit pattern to form an etching resist, and ametal layer on which the etching resist is not formed is etched to forma conductor circuit pattern 40 including the vialands.

The etching solution used in the above process should preferably be atleast one selected from solutions of sulfuric acid-hydrogen peroxide,persulfate, cupric chloride and ferric chloride.

In a pre-processing step for forming the conductor circuit 40 by etchingthe copper foil 12, the entire surface of the copper foil can bepre-etched to reduce the foil thickness to 1 to 10 μm, more preferably,to 2 to 8 μm for easy formation of a fine pattern.

(12) After the conductor circuit 40 is formed on one side of theinsulative substrate 10, processing is effected as in the above steps(2) to (6), and then the PET film 14 is peeled from the surface of theinsulative substrate 10. See FIGS. 6(c) to 6(e).

The height of projection of a projecting conductor 44 formed as in thestep (6) (this projecting conductor is a different one from theprojecting conductor 24 of the double-sided circuit board) from thesurface of the insulative substrate 10 should desirably be substantiallyequal to the thickness of the protective film 14, namely, within a rangeof 5 to 30 μm.

The reason for the above is that if the projecting height is less than 5μm, a poor connection will easily result while if it is more than 30 μm,the resistance will be higher and the projecting conductor 24 willspread too much along the surface of the insulative substrate when it isthermally deformed in the heating and pressing step, resulting inimpossibility of forming a fine pattern.

Also, the projecting conductor 44 should desirably be precured for thereason that it is hard even in the B stage and it will possibly be inelectrical contact with the conductor circuit (conductive pad) of theother circuit board to be stacked along with the circuit board havingthe projecting conductor 44 before the adhesive layer becomes soft arethe steps of stacking and pressing.

The projecting conductor 44 is deformed when heated and pressed to havethe area of contact thereof increased. Thus it can have the electricalresistance thereof lowered and the projecting conductors 44 will havethe variation of height from one to another corrected.

(13) Next, an adhesive resin 46 is applied to the surface of theinsulative substrate 10 including the projecting conductor 44. See FIG.6(f).

The adhesive resin is applied, for example, to over the surface of theinsulative substrate 10 including the projecting conductor 44 or to thesurface not including the projecting conductor 44, and formed as anadhesive layer of a dry non-cured resin. The adhesive layer shouldpreferably be precured since it becomes easier to handle. The adhesivelayer's thickness should desirably be within a range of 5 to 50 μm.

The adhesive layer 46 should desirably be an organic adhesive. It shoulddesirably be at least one selected from epoxy resin, polyimide resin,thermosetting polyphenylether (PPE), a compound of epoxy resin andthermoplastic resin, a compound of epoxy resin and silicon resin, and BTresin.

The non-cured resin being an organic adhesive can be applied using acurtain coater, spin coater, roll coater, spray coater or byscreen-printing. Also, the adhesive layer may be formed by laminating anadhesive sheet,

The single-sided circuit board 50 is formed to have the conductorcircuit 40 provided on one side of the insulative substrate 10, theprojecting conductor 44 whose a part of the conductive paste thereof isexposed, provided on the other side of the insulative substrate 10, andthe adhesive layer 46 provided on the surface of the insulativesubstrate 10 including the projecting conductor 44. A plurality of suchsingle-sided circuit boards is stacked one on the other and bonded toeach other or stacked on and bonded to a previously formed double-sidedcircuit board 34 to form a multilayer printed-circuit board 60. Theadhesive rein 46 should preferably be used in this stacking step.

(B) Making the Multilayer Printed-Circuit Board

Three single-sided circuit boards 50, 52 and 54 are stacked on thedouble-sided circuit board 34 formed through the steps in (A) to providea four-layer assembly. The four-layer assembly is integrated with eachother by a single press-molding at a temperature of 150 to 200° C. undera pressure of 1 to 4 MPa to form the multilayer printed-circuit board60. See FIG. 7.

By the simultaneous pressing and heating under the above conditions, theadhesive layer 46 of each single-sided circuit board is cured to providea strong adhesion between neighboring single-sided circuit boards. Notethat the hot-press should optimally a vacuum hot-press.

In the above embodiment, one double-sided circuit board and threesingle-sided circuit board are used to form a four-layer printed-circuitboard. Note however that the multilayer printed-circuit board mayinclude 5, 6 or more such circuit boards.

(C) Providing the Conductive Dump, Conductive Pin or Ball

On the outermost one of the circuit boards in the multilayerprinted-circuit board formed through the process (B), there is provideda conductive bump on which an electronic component such as LSI chip ismounted. On the other outermost circuit board, there is provided aconductive pin or ball which is connectable directly to a connectionterminal (connector) or a conductive ball on a mother board. Thus, apackage circuit board is constructed.

In the multilayer printed-circuit board 60 shown in FIG. 7 for example,the conductor circuits 40 of the outermost circuit boards 50 and 54 areexposed outside. In this multilayer printed-circuit board, anappropriate solder pad is provided right above each via-hole on eachconductor circuit 40, and an appropriate solder is supplied onto thesolder pad to form a conductive bump 62 or provide a conductive pin 64or conductive ball 66.

Note that the solder used to form the conductive bump 62 shouldpreferably be a tin/lead solder having a relatively low melting point(183° C.) or a tin/silver solder also having a relatively low meltingpoint (220° C.), and the solder to connect the conductive pin 64 orconductive ball 66 should preferably be a tin/antimony solder, atin/silver solder or a tin/sliver/copper solder, each having arelatively high melting point (230 to 270° C.).

In case there is used a multilayer printed-circuit board 80 formed by asingle press-molding, under appropriate heating and pressing conditions,of a four-layer assembly of four single-sided circuit boards 70, 72, 74and 76 stacked one on the other in this order as shown in FIG. 8, theprojecting conductor provided beneath the via-hole on the outermostcircuit board 70 is melted to form a substantially circular conductivepad on the surface of the insulative substrate 10 while a part of theconductor circuit 40 of the other circuit board 76, right above thevia-hole on the conductor circuit 40, is formed as a conductive pad.

In this multilayer printed-circuit board 80, the bottommost circuitboard 70 has connected to the conductive pad beneath the via-holethereon the conductive pin 64 or conductive ball 66 which is to beconnected to a connection terminal or solder ball of a mother board, andthe topmost circuit board 76 has formed on the conductive pad formed apart of the conductor circuit 40 thereof the conductive bump 62 which isto be connected to a solder ball 84 of an electronic component 82 suchas LSI chip.

As indicated with a dash line in FIG. 8, a solder resist layer 83 may beformed on the surfaces of the outermost circuit boards 70 and 76. Inthis case, a solder resist composition is applied to the surface, thefilm of the composition is dried, then a photo mask film on which holesare depicted is placed on the composition film. Then, the compositionmask is exposed to light and developed to form holes in which the solderpad portion of the conductor circuit 40 is exposed, and the conductivebump 62, conductive pin 64 or conductive ball 66 is provided on theexposed solder pad portion.

According to this embodiment, there is provided a semiconductor deviceconsisting of the multilayer printed-circuit board 80 including theconductive pad, pin or ball and the electronic component 82 mounted onthe circuit board 80, or there is provided a semiconductor including themultilayer printed-circuit board 80 including such electronic componentand a mother board to which the circuit board 80 is mounted.

FIG. 10 shows another semiconductor device. In this semiconductordevice, a chip capacitor 86 is connected and secured to the outermostone of the circuit boards 70 of the multilayer printed-circuit board 80while a stiffener 88 to prevent warping is secured along thecircumference of the other outermost circuit board 76.

In this semiconductor device, the chip capacitor 86 is formed from ahighly dielectric material such as ceramic, barium titanate or the likeand electrically connected to the via-hole beneath the electroniccomponent 82 mounted to reduce the loop inductance.

The stiffener 88 is formed from a glass epoxy compound material such asBT, FR4 or FR5 and a metallic material such as copper to prevent warpingof the semiconductor device due to a difference in thermal expansionbetween materials of the circuit boards.

Furthermore, as shown in FIG. 11, the conductive bump 62 is formed onthe conductive pad formed on the conductor circuit 40 of the outermostone of the circuit boards of the multilayer printed-circuit board 80,and the other outermost circuit board (lowest circuit board 70) is soconstructed for no electrolytic copper-plating layer to enter the hole16 formed in the insulative substrate 10. An appropriate solder issupplied to the conductor pad formed on the conductor circuit 40 exposedin the hole 16 to connect the conductive pin 64.

In the above construction, the conductive pin 64 is enclosed by theinsulative substrate 10, and hence no solder resist layer has to beprovided.

In the above embodiment, a metal layer consisting of nickel and goldshould preferably be provided on each solder pad. The nickel layershould preferably be 1 to 7 μm thick and the gold layer be of 0.01 to0.06 μm in thickness for the reason that a thickness of the nickel layerbeing larger than 7 μm will lead to an increased resistance while athickness smaller than 1 μm will lead to an easier peeling from thesolder pad, and a thickness of the metal layer being larger than 0.06 μmwill lead to an increased manufacturing cost while a thickness smallerthan 0.01 μm will lead to a reduced adhesion to the solder pad.

Solder is supplied onto the metal layer of the nickel and gold layersprovided on the solder pad. The supplied solder is melted and solidifiedto form a conductive bump, or the conductive pin or ball is joined tothe solder pad. Thus the multilayer printed-circuit board is formed.

The solder can be supplied to the metal layer by transfer or printing.

The solder transfer is as follows. A solder foil is attached to aprepreg and the solder foil is etched so as to leave not etched only aportion thereof corresponding to the hole, thereby forming a solderpattern in the solder foil. The solder foil having the solder pattern isused as a solder carrier film. After applied with a flux at a portioncorresponding to the hole in the solder resist layer on the substrate,the solder carrier film is laminated on the metal layer for the solderpattern to be in contact with the conductive pad. Then, the soldercarrier film is heated to transfer the solder to the metal layer.

On the other hand, the solder printing is such that a printing maskhaving an opening formed in a position corresponding to the conductivepad (metal mask) is placed on the substrate, a solder paste is printedand heated. The solder used may be a tin-silver alloy, tin-indium alloy,tin-zinc alloy or a tin-bismuth alloy.

(D1) Forming the Single-sided Build-up Wiring Layer

There will be described herebelow an embodiment of the present inventionin which a build-up wiring layer is formed on one side of the multilayerprinted-circuit board 60 formed through the above processes (A) and (B).The double-sided and single-sided circuit boards forming the multilayerprinted-circuit board 60 will not be illustrated for the simplicity ofthe illustration. See FIG. 12(a).

(1) A roughened layer 63 of copper, nickel and phosphorus is formed onthe surface of the conductor layer 40 on one side of the multilayerprinted-circuit board 60 as shown in FIG. 12(b).

The roughened layer 63 is formed from electroless-plating material. Thecopper, nickel and hypophosphorous acid ion concentrations of theelectroless-plating solution should desirably be 2.2×10⁻² to 4.1×10⁻²mol/l, 2.2×10⁻³ to 4.1×10⁻³ mol/l and 0.20 to 0.25 mol/l, respectively.

The above ion concentrations are preferable because the crystallinestructure of a film precipitated in the above solution is a needle-likestructure and has an excellent effect of anchoring. Theelectroless-plating solution may comprise a complexing agent and anadditive in addition to the above compounds.

The roughened layer may be formed by plating with a needle-likecopper-nickel-phosphorus alloy, oxidation-reduction or by etching thecopper surface along the grain boundary.

(2) Next, an interlaminar insulative resin layer 65 is formed on themultilayer printed-circuit board 60 having the roughened layer 63 havingbeen formed in the step (1) above. See FIG. 12(c).

The interlaminar insulative resin layer 65 may be formed by applying aninsulative resin having previously been liquefied by adjustment of itsviscosity by the use of a curtain coater, roll coater or printing,attaching a B-stage insulative resin film or by heating and pressing asheet-formed insulative resin film.

The interlaminar insulative rein layer 60 should desirably be formedfrom at least a one selected from thermosetting resin, thermoplasticresin, photosensitive resin (including ultraviolet-setting resin aswell), thermosetting resin whose part is acrylated, complex ofthermosetting and thermoplastic resins and a complex of photosensitiveand thermosetting resins. In addition, the resin may comprise a curingagent, reaction accelerator, photoreaction polymerizing agent, additiveand a solvent.

The above thermosetting resin may be epoxy resin, phenol resin,polyimide resin, bismaleimide resin, polyphenylene resin, polyolefinresin or fluororesin.

The above epoxy resin may be a novolak type resin such as phenol novolaktype, cresol novolak type, etc., a dicyclopentadiene-denatured alicyclicepoxy resin or the like.

For photosensitization with acryl resin or thermosetting resin by theabove photosensitive resin, the thermosetting group of the thermosettingresin is reacted with methacrylic acid or acrylic acid for acrylation.

The above thermoplastic resin may be a phenoxy resin, polyether sulfon(PES), polysulfone (PSF), polyphenylene sulfide (PPS), polyphenylenesulfide (PPES), polyphenyl ether (PPE) or polyether imnide (PI).

The above resin complexes include a complex of thermosetting andthermoplastic resins and a composite of photosensitive and thermoplasticresins.

The above combination of thermosetting and thermoplastic resins includesa combination of phenolic resin and polyether sulfon, a one of polyimideresin and polysulfon, a one of epoxy resin and polyether sulfon, and aone of epoxy and phenoxy resins.

The above combination of photosensitive and thermoplastic resinsincludes a combination of an epoxy resin whose part of the epoxy groupis acrylated and polyether sulfon, a one of acrylic and phenoxy resins,etc. For the resin complex of thermosetting resin (or photosensitiveresin) and thermoplastic resin, the mixing ratio of them should be 95/5to 50/50 since this ratio can assure a high toughness without loss ofheat resistance.

The interlaminar insulative resin layer 64 may be composed of more thantwo layers. That is, the resin layer may be composed of two differentresins. For example, the amount of the filler may be reduced to improvethe insulation ability and a filler soluble in acid or oxidizer may beimpregnated into the upper layer to improve the adhesion with theelectroless-plating layer. The resin layer should desirably have athickness of 20 to 70 μm. The most preferable thickness is 25 to 50 μmsince it permits to provide an easy solution to both the insulationability and adhesion.

In the above resin film, particles soluble in acid or oxidizer (will bereferred to as “soluble particles” hereafter) are dispersed in arefractory resin. It should be reminded here that the terms “refractory”and “soluble” used herein are defined as follows for the purpose ofdescription of the present invention. That is, a resin which is fastsolved in a solution of acid or oxidizer will be called “soluble resin”while a one slowly solved will be called “refractory resin”.

The soluble particles include for example resin particles soluble inacid or oxidizer (will be referred to as “Isoluble resin particles”hereafter), inorganic particles soluble in acid or oxidizer (will bereferred to as “soluble inorganic particles” hereafter), metal particlessoluble in acid or oxidizer (will be referred to as “soluble metalparticles” hereafter), etc. These soluble particles may be used singlyor two or more of them may be used in combination.

The soluble particles are not limited in shape, but they may beglobular, crushed or in any other shape. The soluble particles shoulddesirably be uniform in shape since they can form a rough surface withirregularities having a uniform roughness.

The mean size of the soluble particles should desirably be 0.1 to 10 μm.In case the particle size is within this range, the soluble particlesmay contain two or more kinds different in size from each other, such assoluble particles whose mean size is 0.1 to 0.5 μm and those whose meansize is 1 to 3 μm. Thereby, it is possible to form more complicatedrough surface, which will assure an improved adhesion to the conductorcircuit. Note that the size of the soluble particles refers herein tothe length of the longest portion of a soluble particle.

The above soluble resin particles include thermoplastic resin particles,thermosetting resin particles, and any other ones soluble faster thanthe above-mentioned refractory resins when dipped in acid or oxidizer.

More specifically, the above soluble resin particles may be formed fromone, or a mixture of two or more, selected from epoxy resin, phenolresin, polyimide resin, polyphenylene resin, polyolefin resin,fluororesin and the like.

Also, the soluble resin particles may be of rubber. The rubber includesfor example polybutadiene rubber, various denatured polybutadienerubbers such as epoxy-denatured, urethane-denatured and(meth)acrylonitrile-denatured ones, (meth)acrylonitrile butadiene rubbercontaining carboxyl group, etc. These rubbers can make the soluble resinparticles more soluble in acid or oxidizer. Namely, the soluble resinparticles can be solved in an acid other than a strong one, and in evenpermanganic acid having a relatively weak oxidizing. Also, the solubleresin particles can be solved in even chromic acid of a lowconcentration. Therefore, no acid or oxidizer will reside on the resinsurface, so there is no likelihood that when a catalyst such aspalladium chloride is added to the formed rough surface, the catalystwill not work or the catalyst will be oxidized.

The above soluble inorganic particles include those formed from at leasta one selected from a group of for example aluminum compound, calciumcompound, potassium compound, magnesium compound and silicide.

The above aluminum compound includes for example alumina, aluminumhydroxide etc., the calcium compound includes for example calciumcarbonate, calcium hydroxide, etc., the potassium compound includes forexample potassium carbonate, etc., the magnesium compound includes forexample magnesia, dolomite, basic magnesium carbonate, etc., and thesilicide includes for example siica, zeolite, etc. These compounds maybe used singly or two or more of them may be used in combination.

The above soluble metal particle may be formed from at least a oneselected from a group of copper, nickel, iron, zinc, gold, silver,aluminum, magnesium, calcium and silicon. Also, to assure an insulation,the soluble metal particles may be covered at the surfaces thereof witha resin or the like.

When two or more of the above-mentioned soluble particles are used asmixed, resin particles and inorganic particles should desirably beselected for combination for the reason that since both the resinparticles and inorganic particles are low in conductivity, a desirableinsulation of the resin film can be assured, the thermal expansion caneasily be adjusted in relation to the refractory resin, no crack willtake place in the interlaminar insulative resin layer formed from theresin film, and no separation will take place between the interlaminarinsulative resin layer and conductor circuit.

The refractory resin is not limited to any special resin since itsuffices to hold the rough surface when acid or oxidizer is used to forma rough surface on the interlaminar insulative resin layer. That is, therefractory resins include for example thermosetting resin, thermoplasticresin and a complex of the thermosetting and thermoplastic resins. Also,the refractory resin may be a photosensitive resin obtained by impartingthe photosensitivity to the thermosetting or thermoplastic resin or thecomplex. Using the photosensitive resin, it is possible to form a holefor via-hole in the interlaminar insulative resin layer by exposure anddevelopment.

Among the above resins, the thermosetting resin is the most desirableone since it allows the rough surface to maintain its shape even whentreated with a plating solution or various steps of heating.

More specifically, the refractory resin includes for example epoxyresin, phenol resin, polyimide resin, polyphenylene resin, polyolefinresin, fluororesin, etc. These resins may be used singly or two or moreof them may be used in combination.

Further, epoxy resin having two or more epoxy groups in one moleculethereof is more desirable for use because it cannot only form theabove-mentioned rough surface but it can prevent stress fromconcentrating on the metal layer even in a heat cycle since it has anexcellent thermal resistance, thus causing no separation of the metallayer.

The above epoxy resin includes for example, epoxy resigns of cresolnovolak type, bisphenol A type, bisphenol F type, phenol novolak type,alkylphenol novolak type, bisphenol F type, naphthalene type anddicyclopentadiene type, epoxy compound being a condensate of phenol andaromatic aldehyde having phenolic hydroxyl group,triglycidihisocyanurate, alicyclic epoxy resin, etc. These resins may beused singly or two or more of them may be used in combination which willassure an improved thermal resistance.

The resin film used herein should desirably be a one in which thesoluble particles are substantially homogeneously dispersed in therefractory resin. This resin film can form a rough surface withirregularities having a uniform roughness. Even if via-holes andthrough-holes are formed in this resin film, the metal layer of theconductor circuit can be formed on the resin film with a high adhesionto the latter. Also, a resin film containing soluble particles may beused only in a surfacial portion on which the rough surface is to beformed. Since this resin film prevents other than the surfacial portionof the resin film from being exposed to acid or oxidizer, the insulationbetween the conductor circuits with the interlaminar insulative resinlayer laid between them can be kept positively.

In the above resin film, the portion of the soluble particles dispersedin the refractory resin should desirably be 3 to 40% by weight of thewhole resin film. If the proportion of the soluble particles is lessthan 3% by weight, the rough surface with desired irregularities cannotbe formed in some cases. On the other hand, if the proportion of thesoluble particles is more than 40% by weight, the soluble particles willbe solved to a depth of the resin film when they are solved in acid oroxidizer, resulting that the insulation between the conductor circuitswith the interlaminar insulative resin layer formed from the resin filmcannot be maintained, which will cause a short-circuit between theconductor circuits.

In the resin film, the soluble particles should desirably contain acuring agent and other compositions in addition to the refractory resin.

The above curing agent includes for example imidazole curing agent,amine curing agent, carbamidine curing agent, epoxy adduct of thesecuring agents, microencapsulation of these curing agents, organicphosphine compound of triphenyl phosphine and tetraphenylphosphonium/tetraphenyl borate, etc.

The content of the curing agent should desirably 0.05 to 10% by weightof the whole resin film. If the content is less than 0.05% by weight,the resin film will not be cured sufficiently so that acid or oxidizerwill infiltrate into the resin film to a higher extent, possiblydegrading the insulation of the resin film. On the other hand, if thecontent is over 10% by weight, the excessive curing agent will possiblymodify the composition of the resin, possibly resulting in a lowerreliability.

The above other compositions include a filler of an inorganic compoundor resin which will not influence the forming of the rough surface. Theinorganic compound includes for example silica, alumina, dolomite, etc.The resin includes for example polyimide resin, polyacryl resin,polyamide imide resin, polyphenylene resin, melanin resin, olefin resin,etc. By mixing any of these fillers in the resin film, it is possible tomatch the coefficient of thermal expansion and improve the heatresistance and chemical resistance, thereby improving the performance ofthe printed wiring board.

Also, the resin film may contain a solvent. The solvent includes forexample ketones such as acetone, methyl ethyl ketone, cyclohexane, etc.and aromatic hydrocarbons such as ethyl acetate, butyl acetate,cellosolve acetate, toluene, xylene, etc. They may be used singly or twoor more of them may be used in combination.

In the present invention, it is desired to use as the interlaminarinsulative resin forming a via-hole 102 which will further be describedlater a to-be-electroless-plated adhesive layer containing a complex ofthermosetting and thermoplastic resins in the form of a matrix. Also, aB-stage resin film may be used as laminated.

(3) After drying the to-be-electroless-plated adhesive layer formed inthe above step (2), a hole 65 a for a via-hole is formed in theinterlaminar insulative resin layer 65. See FIG. 12(d).

When a photosensitive resin is used, it is exposed and developed, andthen thermally set. In case a thermosetting resin is used, it isthermally set and then machined with laser to form the hole 65 a for avia-hole in the adhesive layer (interlaminar insulative resin layer) 65.

(4) Next, the epoxy resin particles existent on the surface of the curedadhesive layer 65 are decomposed or solved in acid or oxidizer forremoval, and the surface of the adhesive layer 65 is roughened toprovide the rough surface 65 b. See FIG. 12(e).

The acid used includes for example phosphoric acid, hydrochloric acid,sulfuric acid or an inorganic acid such as formic acid, acetic acid,etc. Among others, the organic acid is desirably be used since when headhesive layer surface is roughened, the organic acid will not easilyattack the metallic conductor layer exposed in the via-hole.

On the other hand, the oxidizer should desirably be a chromic acid,permanganate (including potassium permanganate etc.) or the lie.

(5) Next, a catalyst nucleus is imparted to the rough surface 65 b ofthe adhesive layer 65.

To impart the catalyst nucleus, noble metal ion and colloid shoulddesirably be used. Generally, palladium chloride and palladium colloidare used. Note that the catalyst nucleus should desirably be heated forfixation. Such a catalyst nucleus should be a palladium.

(6) Further, the surface of the (electroless-plated) adhesive layer 65is electroless-plated to form an electroless-plating layer 67 over theentire rough surface. See FIG. 12(f). At this time, theelectroless-plating layer 67 should preferably be 0.1 to 5 μm, and morepreferably 0.5 to 3 μm.

Next, a plating resist 68 is provided on the electroless-plating layer67. See FIG. 13(a). The plating resist composition should desirably be acomposition of an acrylate of cresol novolak type epoxy resin or phenolnovolak type epoxy resin and an imidazole curing agent. However, acommercially available dry film may be used instead.

(7) Furthermore, a portion, where no plating resist is provided, of theelectroless-plating layer 67 is electro-plated to form a conductor layerwhich is to be on the upper conductor circuit 104 and fill the hole 65 awith an electroplating layer 69 in order to form a via-hole 102. SeeFIG. 12(b).

At this time, the electro-plating layer 67 exposed outside the hole 65 ashould desirably be 5 to 30 μm. The electro-plating material shoulddesirably be a copper.

(8) Moreover, the plating resist 68 is removed, and then theelectroless-plating layer under the plating resist is melted and removedwith a mixed solution of sulfuric acid and hydrogen peroxide or anetching solution of sodium persulfate or ammonium persulfate, to makethe upper conductor circuit 104 and filled via-hole 102 independent ofeach other.

(9) Next, a roughened layer 106 is formed on the surface of the upperconductor circuit 104.

The roughened layer 106 may be formed by etching, polishing, oxidizingand reducing, or plating.

First for the oxidation and reduction, respectively, an oxidation bath(blackening bath) is prepared from 20 g/l of NaOH, 50 g/l of NaClO₂ and15.0 g/l of NaPO₄ and a reduction bath is prepared from 2.7 g/l of NaOHand 1.0 g/l of NaBH₄.

A roughened layer of copper-nickel-phosphorus alloy layer is formed froma precipitate during the electroless-plating.

The electroless-plating solution of the above alloy should desirably bea plating bath of 1 to 40 g/l of copper sulfate, 0.1 to 6.0 g/l ofnickel sulfate, 10 to 20 g/l of citric acid, 10 to 100 g/l ofhypophosphite, 10 to 40 g/l of boric acid, and 0.01 to 10 g/l ofsurfactant.

Furthermore, the surface of the roughened layer 106 is covered with alayer of a metal or noble metal whose reactivity (ionization tendency)is higher than that of copper and lower than that of titanium.

When the above metal is tin, a solution of tin boronfluoride andthiourea or of tin chloride and thiourea is used. At this time, an Snlayer of about 0.1 to 2 μm is produced due to the Cu—Sn substitution.When a noble metal is used, the surface of the roughened layer 106 maybe covered with the noble metal by sputtering or evaporation.

(10) Next, there is formed on the substrate a to-be-electroless-platedadhesive layer 108 as an interlaminar insulative layer.

(11) Further, the above steps (3) to (9) are repeated to form anothervia-hole right above the via-hole 102 (not shown), and provide an upperconductor circuit 110 at a side outer than the upper conductor circuit104. See FIG. 13(c). The surface of the upper conductor circuit 110 andthe surface including the inner wall of the via-hole (not shown) areroughened to form a roughened layer 112.

(12) Next, a solder resist composition 90 is applied to cover theoutermost surface of the build-up wiring layer thus formed, the solderresist layer is dried, a photomask film having holes depicted thereon isplaced over the solder resist layer, and the solder resist layer isexposed and developed to form holes 91 in each of which a conductorportion of the conductor layer, which is to be a solder pad (includingconductive pad and via-hole), is exposed. See FIG. 14(a).

The diameter of the hole 91 may be larger than that of the conductorportion which is to be the solder pad, and the conductor portion may befully exposed. Also, the diameter of the hole 91 may be smaller thanthat of the conductor portion which is to be the solder pad, and thecircumference of the conductor portion may be covered with the solderresist layer 90. In this case, the conductor portion to be the solderpad can be retained by the solder resist layer 90. Thus, preferably, thebuild-up wiring layer should finally be constructed to prevent thesolder pad from separating.

(13) Further, a nickel-hold metal layer is formed on the conductorportion exposed from the hole 91 in the solder resist layer 90 to formthe solder pad.

The nickel layer 92 should desirably be 1 to 7 μm in thickness while thegold layer 94 be 0.01 to 0.06 μm thick. If the nickel layer 92 is toothick, it will lead to an increased resistance. If the nickel layer 92is too thin, it will easily be separable. On the other hand, the goldlayer 94 being too thick will lead to an increased manufacturing costwhile too small a thickness will result in a reduced adhesion to thesolder pad.

(14) Further, solder is supplied onto the conductor circuit (solder pad)exposed from the hole 91 (upper hole) formed in the solder resist layerdisposed at an outermost position of the build-up wiring layer formed onone side of the multilayer printed-circuit board to form a solder bump96, and solder is supplied onto the conductor circuit 110 (solder pad)exposed on the surface of the multilayer printed-circuit board, where nobuild-up wiring layer is formed, to form a T pin 98 or solder ball 100.Thus, a multilayer printed-circuit board is produced. See FIG. 14(b).

The solder may be supplied by transfer or printing.

The solder transfer is as follows. Namely, a solder foil is attached ona prepreg, the solder foil is etched with only a portion thereofcorresponding to the hole being not etched, to form a solder pattern.This solder pattern is taken as a solder carrier film. A flux is appliedto a portion corresponding to the hole in the solder resist layer of thecircuit board, and then the solder carrier film is stacked on the fluxfor the solder pattern to be in contact with the solder pad. The soldercarrier film is heated to transfer the solder to the solder pad. On theother hand, the solder printing is as follows. That is, a printing mask(metal mask) having through-holes formed therein is placed on thecircuit board in a position corresponding to the solder pad, a solderpaste is printed and heated. The solder may be a tin-silver alloy,tin-indium alloy, tin-zinc alloy or a tin-bismuth alloy.

Note that the solder used to form the conductive bump 96 shouldpreferably be a relatively low melting-point tin/lead solder (whichmelts at 183° C.) or tin/silver solder (which melts at 220° C.) and thesolder used to connect a conductive pin 98 and conductive ball 100should preferably be a relatively high melting-point tin/antimonysolder, tin/silver solder or tin/silver/copper solder, whose the meltingpoint is 230 to 270° C.

(D2) Forming Double-sided Build-up Wiring Layer

The core multilayer circuit board 60 formed through the processes (A)and (B) and having the build-up wiring layer formed on either sidethereof is subjected to the steps (1) to (12) for forming thesingle-sided build-up wiring layer as in the process (D1). See FIG.17(a). Then, the solder pad 95 consisting of the nickel layer 92 andgold layer 94 is formed on a portion of the outermost conductor circuit110 of the build-up wiring layer, thereby producing a multilayerprinted-circuit board suitable for use as a mother board. See FIG.17(b).

Further, solder is supplied onto the solder pad 95 formed on theoutermost conductor circuit 110 formed on one side of the double-sidedbuild-up wiring layer to form the solder bump 96, while solder issupplied onto the solder pad 95 formed on the outermost conductorcircuit 110 formed on the other side of the double-sided build-up wiringlayer to provide the T pin 98 or solder ball 100, whereby producing amultilayer printed-circuit board suitable for use as a package circuitboard on which electronic components can be mounted with a high density.See FIG. 18.

The present invention will further be described herebelow concerningexamples thereof.

EXAMPLES Example 1

(1) First, a double-sided circuit board forming a multilayerprinted-circuit board was prepared. The double-sided circuit board useda single-sided coppered laminate, as a starting material, formed byheating and pressing a copper foil and a B-stage prepreg formed byimpregnating a glass cloth with epoxy resin.

The insulative substrate 10 in the single-sided coppered laminate is 75μm thick and the copper foil 12 was 12 μm thick. The adhesive layer of10 μm in thickness was provided on each of the surface where the copperfoil was formed and opposite surface of the laminate, and the PET film14 of 12 μm was laminated on each of the adhesive layers.

(2) Next, the PET film 14 was illuminated with the carbon-dioxide gaslaser to form the hole 1 t for via-hole, extending through the PET film14 and insulative substrate 10 to the copper foil 12, and the inside ofthe hole 16 was illuminated with the ultraviolet laser for the purposeof desmearing.

In this embodiment, the hole for via-hole was formed using a high-peakshort-pulse oscillation type carbon-dioxide gas laser beam machine (byMitsubishi Electric). The glass epoxy resin substrate of 75 μm inthickness, on the resin layer of which the PET film of 22 μm in totalthickness is laminated, was illuminated with a laser beam from the PETfilm side by the mask imaging method to form holes for via-holes of 150μm in diameter at a rate of 100 holes/sec.

Also, to desmear the inside of the hole 16, an ultraviolet laser beammachine using the YAG third harmonic GT605LDX (by Mitsubishi Electric)was used to emit 10 shots of a laser beam at an oscillating frequency of5 kHz and pulse energy of 0.8 mJ.

(3) The substrate thus desmeared was subjected to electrolyticcopper-plating to form the copper foil 12 as a plating lead with a smallgap left at the upper portion of the hole 16. The electrolyticcopper-plating 18 was filled in the hole 16 to form the via-hole 20.

(4) Further, the conductive paste 22 was applied to the copperlayer-plating 18 filled in the hole 16 through the PET film 14 as theprinting mask to form the projecting conductor 24 which projects for thethickness of the PET film 14 from the surface of the insulativesubstrate 10.

(5) Next, the PET film 14 was separated from the surface of theinsulative substrate 10, and then epoxy adhesive was applied to thewhole surface of the projecting conductor 24. The adhesive was dried at100° C. for 30 min to form the adhesive layer 26 having a thickness of20 μm.

(6) The copper foil 28 of 12 μm in thickness was put on the adhesivelayer 26 formed in the step (5), and heated pressed at a temperature of180° C. for 70 min under a pressure of 2 MPa and vacuum of 2.5×10³ Pa.

(7) Thereafter, the copper foils 12 and 28 on both sides of thesubstrate were appropriately etched to form the conductor circuits 30and 32 (including the vialands). Thus the double-sided circuit board 34was prepared.

(8) Next, the single-sided circuit boards to be stacked were prepared.The circuit board used a similar single-sided coppered laminate to thatused in the double-sided circuit board 34.

First, the copper foil 12 of the insulative substrate 10 wasappropriately etched to form the conductor circuit 40, and the PET film14 was laminated on the surface of the insulative substrate 10 oppositeto the side where the conductor circuit 40 was formed.

(9) Thereafter, going through the above steps (2) to (5), the conductorcircuit 40 was formed on one of the surfaces of the insulative substrate10, the electrolytic copper-plating layer 18 was filled into the holeextending from the other surface of the insulative substrate 10 to theconductor circuit 40, the projecting conductor 44 was formed on theelectrolytic copper-plating layer 18, and then the epoxy resin adhesive46 was applied to the surface of the insulative substrate 10 includingthe projecting conductor 44.

The epoxy resin adhesive was precured to for the adhesive layers to bestacked one on the other. Three such single-sided circuit boards 50 werethus prepared.

(10) The double-sided circuit board 34 and three single-sided circuitboards 50, 52 and 54, having been prepared in the above steps (1) to(9), stacked in a predetermined position as shown in FIG. 3, and pressedtogether at a temperature of 180° C. using a vacuum hot press to preparethe multilayer printed-circuit board 60.

(11) Tin/antimony solder whose melting point is about 230° C. was usedto connect the T pin 64 or solder ball 66 to the conductor circuit 40 ofthe lower one (50) of the outermost circuit boards of the multilayerprinted-circuit board 60, and tin/lead solder whose melting point isabout 183° C. was supplied to the conductor circuit 40 of the upper one(54) of the outermost circuit boards to form the solder bump 62, thusproviding a multilayer printed-circuit board. With an electroniccomponent 82 placed on the upper circuit board of the multilayerprinted-circuit board, the tin/lead solder was reflowed at a temperaturenear its melting point to weld the solder ball 84 of the electroniccomponent 82 to the solder bump 62, thus providing a semiconductordevice comprising the multilayer printed-circuit board and electroniccomponent.

Example 2

A multilayer printed-circuit board and semiconductor device wereproduced in the same manner as in the Example 1 except that foursingle-sided circuit boards were stacked in a predetermined position asshown in FIG. 1, and heated and pressed together to form a multilayerprinted-circuit board, and that a solder bump was formed on theconductor circuit (conductor pad) of one outermost circuit board of themultilayer printed-circuit board and the T pin or solder ball was bondedto the solder pad formed by hot-pressing the projecting conductorexposed outside the other outermost circuit board.

Example 3

A multilayer printed-circuit board and semiconductor device wereproduced in the same manner as in the Example 1 except that a solderbump was formed on a solder pad formed on the conductor circuit of oneoutermost one of the four ingle-sided circuit boards, no electrolyticcopper was filled in a hole formed in the insulative substrate of theother outermost circuit board and solder was supplied to a solder padformed on the conductor circuit exposed inside the hole to connect the Tpin (see FIG. 2).

Example 4

A multilayer printed-circuit board and semiconductor device wereproduced in the same manner as in the Example 3 except that a solderresist layer was provided on each of the front and rear outermost onesof four single-sided circuit boards and a solder bump was formed on asolder pad exposed from a hole formed in the solder resist layer (seeFIG. 2).

Example 5

A multilayer printed-circuit board and semiconductor device wereproduced in the same manner as in the Example 3 except that a solderresist layer was provided on each of the front and rear outermost onesof four single-sided circuit boards and a solder bump was formed on asolder pad exposed from a hole formed in the solder resist layer (seeFIG. 1).

Example 6

(1) Following the steps (1) to (10) for the Example 1, there wasprepared a core multilayer circuit board 60 whose L/S=75 μm/75 μm, landdiameter was 250 μm, via-hole diameter was 150 μm, conductor layerthickness was 12 μm and insulative layer thickness was 75 μm.

(2) Next, the core multilayer circuit board 60 having a conductorcircuit 40 formed on either side thereof (see FIG. 15(a)) was dipped inan electroless-plating solution of 8 g/l of copper sulfate, 0.6 g ofnickel sulfate, 15 g/l of citric acid, 29 g/l of sodium hypophosphite,31 g/l of boric acid and 0.1 g/l of surfactant and of which pH=9, tothereby form on the surface of the conductor circuit 40 a 3-μm thickroughened layer 62 of copper, nickel and phosphorus. Then, the substratewas rinsed in water, and dipped in an electroless tin-substitutedplating bath of 0.1 mol/l of tine boric fluoride and 1.0 mol of thioureaat 50° C. for one hour, thereby providing a tin layer of 0.3 μm inthickness on the surface of the roughened layer 63. See FIG. 15(b)(however, the tin layer is not illustrated).

(3) Compositions prepared through the following steps (a) to (b) weremixed together and agitated to prepare an electroless-plating adhesive.

(a) Thirty-five parts by weight of a 25% acrylated product of cresolnovolac type epoxy resin (80% in sold content; 2500 in molecular weight,by Nippon Kayaku Co., Ltd.), 4 parts by weight of photosensitive monomer(ALLONIX M315 by Toa Gosei Co., Ltd.), 0.5 part by weight ofantifoarming agent (S-65 by SANNOPCO) and 3.6 parts by weight of NMP,were mixed by agitation.

(b) Eight parts by weight of polyether sulfone (PES) and 7.245 parts byweight of epoxy resin particles (POLYMERPOL by Sanyo Kasei Co., Ltd.) of0.5 μm in mean particle size were mixed together and then 20 parts byweight of NMP were added to the mixture. They were mixed by agitation.

(c) Two parts by weight of imidazole curing agent (2E4MZ-CN by ShikokuKasei Co., Ltd.), 2 parts by weight of initiator (IRGACURE I-907 byChiba Geigie), 0.2 part by weight of photosensitizer (DETX-S by NipponKayaku Co., Ltd.) and 1.5 parts by weight of NMP were mixed together byagitation.

(4) The electroless-plating adhesive prepared in the step (3) above wasapplied to the substrate 60 processed in the step (2) (see FIG. 15(c)),and dried to form an adhesive layer. A photomask film having blackcircles of 85 μm in diameter printed thereon was closely attached toeither side of the substrate 60 where the dry adhesive layer was formed,and then exposed to a light of 500 mJ/cm² from an ultrahigh voltagemercury lamp. A solution of DMDG (diethylene glycol dimethyl ether) wassprayed to the photomask film and developed to form in the adhesivelayer a hole 65 a of 85 μm which becomes a via-hole. Further, thesubstrate was exposed to a light of 3000 mJ/cm² from the ultrahighvoltage mercury lamp, and heated at a temperature of 100°C. for 1 hour,and then at a temperature of 150° C. for 5 hours to form an interlaminarinsulative substrate 65 (adhesive layer) of 35 μm in thickness, havinghigh-precision holes corresponding to the black circles in the photomaskfilm (see FIG. 15(d)). Note that the tin-plating layer was partiallyexposed in the hole 65 a for via-hole.

(5) The substrate having the holes for via-holes 65 formed therein wasdipped in a chromic acid solution for 20 min to solve and remove epoxyresin particles from the adhesive layer surface and roughen the surfaceof the adhesive layer 65 to a depth of about R_(max)=1 to 5 μm to form aroughened surface 65 b, and thereafter dipped in a neutralizationsolution (by Siplay) and then rinsed in water.

(6) By adding a palladium catalyst (by ATOTEK) to the roughened layer 65b (roughened depth of 3.5 μm) on the adhesive layer surface, catalystnucleus was imparted to the surfaces of the adhesive layer 65 and holes65 a for via-holes.

(7) The substrate was dipped in an electroless-plating bath whosecomposition is as follows to form an electroless copper-plating layer 67of 0.6 μm in thickness on the whole rough surface (see FIG. 15(f)). Atthis time, there were found on the surface of the electrolesscopper-plating layer 67 the irregularities following those of the roughsurface 65 b of the adhesive layer 65 since the layer was thin.

Electroless-plating Solution

NiSO4 0.003 mol/l Tartaric acid 0.20 mol/l Copper sulfate 0.03 mol/lHCHO 0.05 mol/l NaOH 0.10 mol/l α, α′-bipyridyl 40 mg/l polyethyleneglycol (PEG) 0.1 g/l [Electroless-plating conditions] Solutiontemperature 33° C.

(8) A commercially available photosensitive dry film was attached to theelectroless copper-plating layer 67 formed in the step (7) above, and amask was placed on the film, exposed to a light of 100 mJ/cm², anddeveloped with in a 0.8% sodium carbonate solution to form a platingresist 68 of 15 μm in thickness. See FIG. 16(a).

(9) Next, a portion where no plating resist was formed waselectro-plated under the following conditions to form an electro-platinglayer 69 of 20 μm in thickness and provide a conductor layer where anupper conductor circuit 104 is to be formed, and form a via-hole 102from the hole filled with a plating layer 69. See FIG. 16(b).

Electro-plating Solution

CuSO₄ · 5H₂O 60 g/l Leveling agent (HL by ATOTEK) 40 ml/l Sulfuric acid190 g/l Brightening agent (UV by ATOTEK) 0.5 ml/l Chlorine ion 40 ppm

Electro-plating Conditions

Bubbling 3.0 liters/min Current density 0.5 A/dm² Set current value 0.18A Plating length of time 130 min

(10) After the plating resist 68 was separated and removed, theelectroless-plating layer 67 under the plating resist was melted andremoved using a mixed solution of sulfuric acid and hydrogen peroxide oran etching solution of sodium persulfate or ammonium persulfate, to forman upper conductor circuit 104 consisting of the electroless-platinglayer 67 and electrolytic copper-plating layer 69 and whose thicknesswas about 20 μm and L/S=25 μm/25 μm. At this time, the surface of thevia-hole 102 was flat and the conductor circuit surface was level withthe via-hole surface.

(11) A roughened layer 84 was formed on the substrate as in the abovestep (2), and the steps (3) to (10) were repeated to further form anupper interlaminar insulative resin layer 108 and conductor circuit 110(including via-hole 80). Thus, a build-up wiring layer was formed oneither side of the multilayer printed circuit board 60.

Note that the roughened layer 112 of copper, nickel and phosphorus wasformed on the surface of the conductor circuit 110 but notin-substituted plating layer was formed on the surface of the roughenedlayer 112.

(12) On the other hand, a solder resist composition was prepared bymixing 46.67 parts by weight of a photosensitive oligomer (4000 inmolecular weight) produced by acrylating 50% of epoxy group of a 60% byweight of cresol novolak type epoxy resin (by Nippon Kayaku Co., Ltd.)solved in DMDG (diethylene glycol dimethyl ether), 14.121 parts byweight of a 80% by weight of bisphenol A type epoxy resin (EPICOAT 1001by YUKA SHELL) solved in methyl ethyl ketone, 1.6 parts by weight ofimidazole (2E4MZ-CN by SHIKOKU KASEI), 1.5 parts by weight of apolyvalent acryl monomer being a photosensitive monomer (R604 by NipponKayaku), 30 parts by weight of a same polyvalent acryl monomer (DPE6A byKYOEISHA KAGAKU), and 0.36 part by weight of leveling agent made from anacrylic ester polymer (POLYFLOW No. 75 by KYOEISHA KAGAKU), adding tothis mixture 20 parts by weight of benzophenone as initiator (by KANTOKAGAKU) and 0.2 part by weight of EAB as photosensitizer (by HODOGAYAKAGAKU), and further adding 10 parts of weight of DMDG (diethyleneglycol dimethyl ether) to the mixture to adjust the viscosity to 1.4±0.3Pa·s at 25° C.

Note that the viscosity of the solder resist composition was measuredusing a B-type viscometer (DVL-B by Tokyo Keiki). For 60 rpm, No. 4rotor was used with the viscometer. For 6 rpm, No. 3 rotor was used.

(13) The solder resist composition obtained in the step (12) was appliedto a thickness of 20 μm on either side of the build-up wiring layerformed in the step (11). Next, the substrate was dried at 70° C. for 20min, and then at 70° C. for 30 min, a soda lime glass substrate of 5 mmin thickness and having a chromium layer in which a pattern of circlesfor holes which were to be formed in the solder resist layer wasdepicted was exposed to an ultraviolet of 1000 mJ/cm² and developed inDMTG with the chromium layer closely attached to the solder resistlayer. Further, the substrate was heated at 80° C. for 1 hour, 100° C.for 1 hour, 120° C. for 1 hour and at 150° C. for 3 hours to form asolder resist layer 90 (of 20 μm in thickness) whose pad portions areopened (to a diameter of 200 μm).

(14) Next, the substrate having the solder resist layer 90 formedthereon was dipped in an electroless nickel-plating solution of 30 g/lof nickel chloride, 10 g/l of sodium hypophosphite and 10 g/l of citricacid and whose pH=5 for 20 min to form a nickel-plating layer 92 of 5 μmin thickness at each hole. Further, the substrate was dipped in anelectroless-plating solution of 2 g/l of potassium gold cyanide and 5g/l of ammonium chloride, sodium citrate at 93° C. for 23 sec to form agold-plating layer 94 of 0.03 μm in thickness on the nickel-platinglayer 92.

Thereby, a solder pad 94 consisting of the nickel-plating layer 92 andgold-plating layer 94 was formed on the upper conductor layer 112, toprepare a multilayer printed circuit board suitably for use as a motherboard having three single-sided circuit boards or six double-sidedcircuit boards. See FIG. 17(b).

In the multilayer printed-circuit board produced as in the above, theland of the via-hole in the core multilayer circuit board can be formedcircular and the lands can be formed at a pitch of 600 μm. So, thevia-holes can easily be formed with a high density. Also since anincreased number of via-holes can be formed in the core multilayercircuit board, the conductor circuit in the core multilayer circuitboard can electrically be connected to the conductor circuit in abuild-up wiring board with a high reliability.

Further, the conductive ball (solder ball) on the package circuit boardon which electronic components including semiconductor chips such as LSIis connected to the solder pad 95 provided at an outermost position ofthe build-up wiring layer. So, the package circuit board is advantageousfor mounting of electronic components.

Example 7

A multilayer printed-circuit board was produced by forming the solderbump 96 on the solder pad 95 formed on one outermost upper conductorcircuit 112 of the multilayer printed-circuit board produced as in theembodiment 6, and providing the T pint 98 or solder ball 100 on thesolder pad 95 formed on the other outermost upper conductor circuit 112.See FIG. 18.

An electronic component such as LSI chip is connected to the multilayerprinted-circuit board thus produced by means of the solder bump 96provided onr the gold-plating layer 94 (solder pad) exposed from thehole in the solder resist layer 90 provided above the build-up wiringlayer, and also the multilayer printed-circuit board is connected to theconnection terminals of a mother board by means of the conductive pin 98or conductive ball 100 provided on the gold-plating layer 94 (solderpad) exposed from the hole in the solder resist layer 90 provided underthe build-up wiring layer.

Example 8

A multilayer printed-circuit board was produced in the same manner as inthe Example 6 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-holes andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

Example 9

A multilayer printed-circuit board was produced in the same manner as inthe Example 6 except that an interlaminar insulative resin layer wasformed by heating and pressing an epoxy resin film of 20 μm inthickness, forming via-hole-oriented holes of 60 μm in diameter byirradiating a carbon dioxide gas laser to the epoxy resin film androughening the surface of the interlarninar insulative resin layerincluding the wall surface of the holes with a permanganic acidsolution.

The epoxy resin film should desirably be a complex with a phenoxy resin,and it contained particles for forming a roughened layer.

Example 10

A multilayer printed-circuit board was produced in the same manner as inthe Example 9 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-holes andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

Example 11

A multilayer printed-circuit board was produced in the same manner as inthe Example 6 except that a polyolefin resin film of 20 μm in thicknesswas heated and pressed to the interlarninar insulative resin layer, acarbon dioxide gas laser is irradiated to the polyolefin resin film toform via-hole-oriented holes of 60 μm in diameter, then anelectroless-plating layer is formed while no surface roughening is done,and a copper sputtered layer or copper-nickel sputtered layer of 0.1 μmin thickness was formed by sputtering on the surface of the interlaminarinsulative resin layer including the hole inner-wall surface.

Example 12

A multilayer printed-circuit board was produced in the same manner as inthe Example 11 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-hole s andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

Example 13

(1) Following the steps (1) to (10) for the Example 1, a core multilayercircuit board 60 was prepared of which LIS=75 μm/75 μm, land diameterwas 250 μm, via-hole diameter was 150 μm, conductor layer thickness was12 μm and insulative layer thickness was 75 μm.

(2) Next, the core multilayer circuit board having the conductor circuit40 formed on either side thereof (see FIG. 12(a)) was subjected at oneside thereof to the steps (2) to (14) for the Example 6 to form abuild-up wiring layer on one side of the core multilayer circuit board60, and form the solder pad 95 consisting of the nickel-plating layer 92and gold-plating layer 94, exposed in the hole 91 in the solder resistlayer 90 covering the upper conductor circuit 112.

(3) The solder bump 96 was formed on the solder pad 95, T pin 98 orsolder ball 100 was provided on the conductor circuit 40 of themultilayer printed-circuit board 60, where no build-up wiring layer wasformed, to thereby produce a multilayer printed-circuit board includingthree single-sided circuit boards, suitable for use as a package circuitboard. See FIG. 14(b).

Example 14

A multilayer printed-circuit board was produced in the same manner as inthe Example 13 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-holes andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

Example 15

A multilayer printed-circuit board was produced in the same manner as inthe Example 13 except that an interlaminar insulative resin layer wasformed by heating and pressing an epoxy resin film of 20 μm inthickness, forming via-hole-oriented holes of 60 μm in diameter byirradiating a carbon dioxide gas laser to the epoxy resin film androughening the surface of the interlaminar insulative resin layerincluding the wall surface of the holes with a permanganic acidsolution.

The epoxy resin film should desirably be a complex with a phenoxy resin,and it contained particles for forming a roughened layer.

Example 16

A multilayer printed-circuit board was produced in the same manner as inthe Example 15 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-holes andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

Example 17

A multilayer printed-circuit board was produced in the same manner as inthe Example 13 except that a polyolefin resin film of 20 μm in thicknesswas heated and pressed to the interlaminar insulative resin layer, acarbon dioxide gas laser is irradiated to the polyolefin resin film toform via-hole-oriented holes of 60 μm in diameter, then anelectroless-plating layer is formed while no surface roughening is done,and a copper sputtered layer or copper-nickel sputtered layer of 0.1 μmin thickness was formed by sputtering on the surface of the interlaminarinsulative resin layer including the hole inner-wall surface.

Example 18

A multilayer printed-circuit board was produced in the same manner as inthe Example 17 except that a conductive paste is filled intovia-hole-oriented bores formed in the double- and single-sided circuitboards of the multilayer printed-circuit board to form via-holes andconductive paste is supplied onto the via-holes as in the same manner asin forming of the via-holes to form projecting conductors.

COMPARATIVE EXAMPLES

(1) An insulative substrate formed from a double-sided coppered laminateof 0.8 μm in thickness was used as a core substrate. A through-hole of300 μm in diameter was drilled in the core substrate using a drill, thenthe core substrate was electroless-plated and electro-plated to form aconductor layer including the through-holes, and a roughened layer wasprovided on the entire surface of the conductor layer, a non-conductivefiller was filled in the through-hole, dried and cured.

(2) Next, runover of the filler flash from the through-hole was removed,and the through-hole circumferential edge was flattened and thickenedwith an electroless-plating material and electroplating material appliedthereto for forming parts which were to be a conductor circuit and aconductor layer which was to cover the filler filled in thethrough-hole.

(3) An etching resist was formed on the surface of the substrate onwhich the parts to be the conductor circuit and conductor layer coveringthe filler filled in the through-hole, the plating layer on which noetching resist was formed was removed by etching, and the etching resistwas separated and removed to form an independent conductor circuit and aconductor layer which covered the filler.

Further, following the steps (2) to (14) for the Example 4, a multilayerprinted-circuit board was prepared.

The Examples 1 to 5 were examined for the length of wiring from theelectronic component such as LSI chip to the solder bump, BGA (ball gridarray) or PGA (pin grid array), number of lands formed, and total areaof the lands for comparison with the conventional printed wiring boards.As the result, it was found that the wiring length in the Examples 1 to5 was {fraction (8/10)} to ½ of that in the conventional printed wiringboards, the number of lands formed was 1.5 to 2.0 times larger, and thatthe land area was ⅔ to {fraction (8/10)} of that in the conventionalprinted wiring boards, which proved that a high wiring density can beattained in the Examples 1 to 5. Especially, the Examples 4 and 5 werefound to have an improved insulation as a package circuit board.

The Examples 6 to 18 were examined for the length of wiring from theelectronic component such as LSI chip to the solder bump, BGA (ball gridarray) or PGA (pin grid array) and the number of lands for comparisonwith the Comparative examples. The result of examination showed that thewiring length was 10 to 25% shorter than that in the Comparativeexamples, the number of core lands per unit area (cm²) was 10 to 30%larger and that there were nothing affecting adversely the electricalproperties and reliability of the Examples 6 to 18.

INDUSTRIAL APPLILCABILITY

As having been described in the foregoing, the present inventionprovides a multilayer printed-circuit board formed by heating andpressing together a plurality of single- or double-sided circuit boards,as a basic part, having a conductor circuit formed on one or either sideof a hard insulative substrate, and via-holes formed by filing aconductive substance into a fine hole formed by illuminating with alaser from a surface of the hard insulative substrate opposite to theside on which the conductor circuit is formed. In the multilayerprinted-circuit board, the wiring density can be considerably elevated.Since the circuit boards can be electrically connected to each other viathe filled via-holes, without any through-holes, with a sufficientreliability, the multilayer printed-circuit board according to thepresent invention can be suitably used as a package circuit board onwhich electronic components such as LSI chip are to be mounted.

Further, the present invention provides a multilayer printed-circuitboard using the above multilayer printed-circuit board as a core andhaving a build-up wiring layer provided on one or either side of thecore multilayer circuit board. This multilayer printed-circuit board canadvantageously be used not only as a package circuit board but as amother board on which a packet board is mounted.

According to the present invention, a conductive bump is formed on oneoutermost circuit board of the multilayer printed-circuit board while aconductive pin or ball is provided on the other outermost circuit board.Namely, this construction is optimum for a package circuit board. Sinceconductive bumps, conductive pins or balls for electrical connectionwith electronic pacts or mother board can be formed with a high density,wiring can be made with a high density and also electronic componentscan be mounted with a high density. Also, since the multilayerprinted-circuit board according to the present invention is constructedto moderate the stress, the wiring will not warp and the flatness of theT pins and conductive bumps can be assured.

What is claimed is:
 1. A multilayer printed-circuit board formed bystacking a plurality of circuit boards on each other, each of saidplurality of circuit boards including a hard insulative substratecomprising two sides, and at least one conductor circuit formed on atleast one of said two sides, and a plurality of via-holes eachcomprising a hole formed through the hard insulative substrate extendingto the at least one conductor circuit, and each filled with a conductivesubstance; applying an adhesive between the plurality of circuit boards,and heating and pressing the plurality of circuit boards togetherforming stacked circuit boards having two outermost circuit boards; oneof the outermost circuit boards having formed on the surface thereof atleast one conductive bump positioned right above a via-hole andelectrically connected to the via-hole; the other outermost circuitboard having formed on the surface thereof at least one conductive pinor ball positioned right above a via-hole and electrically connected tothe via-hole; and a distance between neighboring via-holes formed ineach of the circuit boards increases from one circuit board to another.2. The multilayer printed-circuit board as set forth in claim 1, whereinone of the outermost circuit boards has formed on the surface thereof asolder resist layer covering the at least one conductor circuit, andright above the via-hole at least one conductive bump connecting to aconductive layer or via-hole exposed from a hole formed in the solderresist layer, and the other outermost circuit board has formed on thesurface thereof a solder resist layer covering the at least oneconductor circuit, and right above the via-hole at least one conductivepin or ball connecting to a conductive layer or via-hole exposed from ahole formed in the solder resist layer.
 3. The multilayer printedcircuit board as set forth in claim 1, wherein the conductive substancefilled in the via-hole in each of the circuit boards forming togetherthe multilayer printed-circuit board is a metal-plating layer formed byelectro-plating, and at least one projecting conductor is electricallyconnected to the metal-plating layer.
 4. The multilayer printed-circuitboard as set forth in claim 3, wherein the projecting conductor isformed from a conductive paste.
 5. The multilayer printed circuit boardas set forth in claim 1, wherein the conductive substance filled in thevia-hole in each of the circuit boards forming together the multilayerprinted-circuit board is a conductive paste comprising metal particlesand thermosetting or thermoplastic resin.
 6. A semiconductor deviceincluding the multilayer printed-circuit board according to claim 1 andat least one electronic component electrically connected to the at leastone conductive bump formed on the one of the outermost circuit boards ofthe multilayer printed-circuit board.
 7. The semiconductor device as setforth in claim 6, wherein the circuit board on which at least oneelectronic component is mounted has a stiffener along the circumferencethereof and at least one chip capacitor is electrically connected to thesurface of the other outermost circuit board opposite to the outermostcircuit board on which the at least one electronic component is mounted.8. A multilayer printed-circuit board formed by stacking on each other:a plurality of single-sided circuit boards, each including a hardinsulative substrate having at least one conductor circuit formed on oneside thereof, and a plurality of via-holes each comprising a hole formedthrough the hard insulative substrate extending to the at least oneconductor circuit, and each filled with a conductive substance; and asingle-sided circuit board including a hard insulative substrate havingat least one conductor circuit formed on one side thereof, and at leastone through-hole formed through the hard insulative substrate extendingto the at least one conductor circuit; and applying an adhesive betweenthe single-sided circuit boards, and heating and pressing thesingle-sided circuit boards together forming stacked circuit boardshaving two outermost circuit boards; one of the outermost circuit boardshaving formed on the surface thereof at least one conductive bumppositioned right above a via-hole and electrically connected to thevia-hole; and the other outermost circuit board having formed on thesurface thereof at least one conductive pin or ball positioned rightabove a via-hole and electrically connected to the via-hole; and adistance between neighboring via-holes formed in each of the circuitboards increases from one circuit board to another.
 9. The multilayerprinted circuit board as set forth in claim 8, wherein the conductivesubstance filled in the via-holes in each of the circuit boards formingtogether the multilayer printed-circuit board is a metal-plating layerformed by electro-plating, and at least one projecting conductor iselectrically connected to the metal-plating layer.
 10. The multilayerprinted circuit board as set forth in claim 8, wherein the conductivesubstance filled in the via-holes in each of the circuit boards formingtogether the multilayer printed-circuit board is a conductive pastecomprising metal particles and thermosetting or thermoplastic resin. 11.A semiconductor device including the multilayer printed-circuit boardaccording to claim 8 and at least one electronic component electricallyconnected to the at least one conductive bump formed on the one of theoutermost circuit boards of the multilayer printed-circuit board.
 12. Amultilayer printed-circuit board including a core multilayer circuitboard having two sides and at least one inner conductor circuit, abuild-up wiring layer formed on at least one of said two sides and frominterlaminar insulative resin layers and conductor layers alternatelystacked on each other, the conductor layers being connected to eachother by at least one via-hole, the core multilayer circuit board beingformed by stacking a plurality of circuit boards on each other, each ofsaid plurality of circuit boards including a hard insulative substratecomprising two sides, and at least one conductor circuit formed on atleast one of said two sides, and a plurality of via-holes eachcomprising a hole formed through the hard insulative substrate extendingto the at least one conductor circuit, and filled with a conductivesubstance; and applying an adhesive between the plurality of circuitboards; a distance between neighboring via-holes formed in each of thecircuit boards increases from one circuit board to another and said coremultilayer circuit board having no through-holes penetrating theplurality of circuit boards.
 13. The multilayer printed-circuit board asforth in claim 12, wherein the build-up wiring layer is formed on bothsides of the core multilayer circuit board, an outermost conductor layerforming one of the build-up wiring layers having at least one solderbump formed on the surface thereof and another outermost conductor layerforming the other build-up wiring layer having at least one conductivepin or ball formed on the surface thereof.
 14. The multilayerprinted-circuit board as set forth in claim 12, wherein the build-upwiring layer is formed on both sides of the core multilayer circuitboard, and outermost conductor layers forming the build-up wiring layerbeing covered with a solder resist layer and at least a part of theoutermost conductor layer exposed from the hole formed in the solderresist layer being formed as a conductor pad or in the form of aconnection terminal.
 15. The multilayer printed-circuit board as setforth in claim 12, wherein the conductive substance is a metal-platinglayer formed by electroplating and at least one projecting conductor isformed and electrically connected to the metal-plating layer.
 16. Themultilayer printed-circuit board as set forth in claim 15, wherein theprojecting conductor is formed from a conductive paste.
 17. Themultilayer printed-circuit board as set forth in claim 12, wherein theconductive substance is a conductive paste comprising metal particlesand thermosetting or thermoplastic resin.
 18. The multilayerprinted-circuit board as set forth in claim 12, wherein a part of thevia-holes in the build-up wiring layer is positioned right above thevia-holes formed in the core multilayer circuit board and connecteddirectly to the via-holes.
 19. The multilayer printed-circuit board asset forth in claim 12, wherein the insulative substrate of each of thecircuit boards forming together the core multilayer circuit boardcomprises one of glass epoxy resin, glass bismaleimide-triazine resin,glass polyphenylene ether resin, aramid non-woven fabric-epoxy resin andaramid non-woven fabric-polyimide resin.
 20. The multilayerprinted-circuit board as set forth in claim 19, wherein the insulativesubstrate of each of the circuit boards forming together the coremultilayer circuit board is formed from a glass epoxy resin of 20 to 100μm in thickness and each filled via-hole has a diameter of 50 to 250 μm.21. The multilayer printed-circuit board as set forth in claim 20,wherein the at least one via-hole in each of the circuit boards formingtogether the core multilayer circuit board is formed from a hole formedby illuminating the surface of the glass epoxy resin substrate with 1 to50 shots of a carbon-dioxide gas laser whose pulse energy is 0.5 to 100μmJ, pulse width is 1 to 100 μs, pulse interval is 0.5 ms or more.
 22. Amultilayer printed circuit board as set forth in claim 12, wherein thehard insulative substrate of each of the circuit boards forming togetherthe core multilayer circuit board is formed from resin impregnated glasscloth material.
 23. A semiconductor device including a multilayerprinted-circuit board formed by stacking a plurality of circuit boardson each other, each of said plurality of circuits boards including ahard insulative substrate comprising two sides, and at least oneconductor circuit formed on at least one of said two sides, a pluralityof via-holes each comprising a hole formed through the hard insulativesubstrate extending to the at least one conductor circuit, and eachfilled with an electro-plating substance, and including at least oneprojecting conductor electrically connected to the via-hole; applying anadhesive between the plurality of circuit boards, and heating andpressing the circuit boards together forming stacked circuit boardshaving two outermost circuit boards, and electrically connecting atleast one electronic component to one of said two outermost circuitboards of the multilayer printed-circuit board; one of the outermostcircuit boards having formed on the surface thereof at least oneconductive bump positioned right above a via-hole and electricallyconnected to the via-hole, and the electronic component beingelectrically connected to the at least one conductive bump; the otheroutermost circuit board opposite to the outermost circuit board on whichthe electronic component is mounted including on the surface thereof atleast one chip capacitor electrically connected to the via-holepositioned beneath the electronic component; and a distance betweenneighboring via-holes formed in each of the circuit boards increasesfrom one circuit board to another.
 24. The semiconductor device as setforth in claim 23, wherein the circuit board on which the electroniccomponent is mounted has a stiffener secured by bonding to thecircumference thereof.
 25. The semiconductor device as set forth inclaim 23, wherein the at least one electronic component comprises an LSIchip.
 26. A multilayer printed-circuit board formed by stacking aplurality of circuit boards on each other, each of said plurality ofcircuit boards including a hard insulative substrate comprising twosides, and at least one conductor circuit formed on at least one of saidtwo sides, and a plurality of via-holes each comprising a hole formedthrough the hard insulative substrate extending to the at least oneconductor circuit, and each filled with a conductive substance; applyingan adhesive between the plurality of circuit boards, and heating andpressing the plurality of circuit boards together forming stackedcircuit boards having two outermost circuit boards; one of the outermostcircuit boards having formed on the surface thereof at least oneconductive bump positioned right above a via-hole and electricallyconnected to the via-hole; the other outermost circuit board havingformed on the surface thereof at least one conductive pin or ballpositioned right above a via-hole and electrically connected to thevia-hole; and a density with which the via-holes are formed in each saidstacked circuit boards being smaller from the one of the outermostcircuit boards on which an electronic component is to be mounted towardsthe other outermost circuit board adapted to be connected to a motherboard.
 27. A multilayer printed-circuit board formed by stacking on eachother: a plurality of single-sided circuit boards, each including a hardinsulative substrate having at least one conductor circuit formed on oneside thereof, and-a plurality of via-holes each comprising a hole formedthrough the hard insulative substrate extending to the at least oneconductor circuit, and each filled with a conductive substance; and asingle-sided circuit board including a hard insulative substrate havingat least one conductor circuit formed on one side thereof, and at leastone through-hole formed through the hard insulative substrate extendingto the at least one conductor circuit; and applying an adhesive betweenthe single-sided circuit boards, and heating and pressing thesingle-sided circuit boards together forming stacked circuit boardshaving two outermost circuit boards; one of the outermost circuit boardshaving formed on the surface thereof at least one conductive bumppositioned right above a via-hole and electrically connected to thevia-hole; and the other outermost circuit board having formed on thesurface thereof at least one conductive pin or ball positioned rightabove a via-hole and electrically connected to the via-hole; and adensity with which the via-holes are formed in each said stacked circuitboards being smaller from the one of the outermost circuit boards onwhich an electronic component is to be mounted towards the otheroutermost circuit board adapted to be connected to a mother board.
 28. Asemiconductor device including a multilayer printed-circuit board formedby stacking a plurality of circuit boards one each other, each of saidplurality of circuits boards including a hard insulative substratecomprising two sides, and at least one conductor circuit formed on atleast one of said two sides, a plurality of via-holes each comprising ahole formed through the hard insulative substrate extending to the atleast one conductor circuit, and each filled with an electro-platingsubstance, and including at least one projecting conductor electricallyconnected to the at least one via-hole; applying an adhesive between theplurality of circuit boards, and heating and pressing the circuit boardstogether forming stacked circuit boards having two outermost circuitboards, and electrically connecting at least one electronic component toone of said two outermost circuit boards of the multilayerprinted-circuit board, one of the outermost circuit boards having formedon the surface thereof at least one conductive bump positioned rightabove a via-hole and electrically connected to the via-hole, and theelectronic component being electrically connected to the at least oneconductive bump; the other outermost circuit board opposite to theoutermost circuit board on which the electronic component is mountedhaving on the surface thereof at least one chip capacitor electricallyconnected to the via-hole positioned beneath the electronic component;and a density with which the via-holes are formed in each said stackedcircuit boards being smaller from the one of the outermost circuitboards on which an electronic component is to be mounted towards theother outermost circuit board adapted to be connected to a mother board.